Nonvolatile semiconductor memory device and method of self-testing the same

A nonvolatile semiconductor storage device comprising:

• a plurality of memory cell blocks in which a plurality of memory cells which store information are arranged;
• a test interface which receives a test command designating execution of a test for said plurality of memory cell blocks;
• a plurality of test storage circuits which store test information necessary to execute the test designated by the test command, each of said plurality of test storage circuits comprising an erasable programmable storage unit;
• a decoder which decodes the test command input to the test interface, and selects a specific test storage circuit from said plurality of test storage circuits on the basis of a decoding result;
• a sense amplifier which reads out the test information from the test storage circuit selected by the decoder;
• a holding circuit which holds the test information read out by the sense amplifier;
• a control circuit which controls a test operation of checking whether said plurality of memory cell blocks normally operate, on the basis of the test information held in the holding circuit;
• and
• a plurality of defective block storage circuits arranged in one-to-one correspondence with said plurality of memory cell blocks, each of said plurality of defective block storage circuits storing fail information indicating that a memory cell block is defective if the memory cell block does not normally operate in the test operation performed by the control circuit.

A method of self-testing a nonvolatile semiconductor memory device, comprising:

• writing test information necessary to execute a test to be designated by a test command and conducted on a memory cell, in a test storage circuit comprising an erasable programmable storage unit;
• inputting the test command to a test interface;
• selecting the test information from the test storage circuit in accordance with the input test command;
• reading out the selected test information from the test storage circuit and holding the readout test information;
• controlling a test operation of checking whether the memory cell normally operates, on the basis of the held test information;
• storing, in a defect storage circuit, fail information indicating that the memory cell is defective, if the memory cell does not normally operate in the test operation;
• replacing the defective memory cell with a redundancy memory cell if the fail information is stored in the defect storage circuit;
• and
• storing an address of the defective memory cell replaced with the redundancy memory cell in a redundancy circuit.