Static memory cell having independent data holding voltage

A semiconductor device using a static memory cell which includes a plurality of MOS transistors having gates and drains cross-coupled to each other and which is coupled to a word line and a data line,

• wherein a power supply node of the static memory cell is coupled to a first supply voltage by a voltage supplier lying out of the static memory cell,
• wherein the first supply voltage is larger than a maximum voltage to be applied to the data line,
• wherein the static memory cell includes a plurality of static memory cells, and
• wherein a common supply voltage line belonging commonly to the plurality of static memory cells is divided into sub supply voltage lines and a voltage to be applied to the common supply voltage line is controlled by the sub supply voltage lines.

A semiconductor device, comprising:

• a static memory cell including a plurality of first MOS transistors having gates and drains cross-coupled to each other;
• a data line coupled to the static memory cell;
• and
• a peripheral circuit being coupled to the data line and including a plurality of second MOS transistors,
• wherein the plurality of first MOS transistors have a threshold voltage larger than that of the plurality of second MOS transistors,
• wherein an internal supply voltage of the static memory cell is controlled in a state that the static memory cell is selected.

A semiconductor device comprising:

• a plurality of input/output terminals;
• a first circuit coupled to said plurality of input/output terminals;
• and
• a second circuit coupled to said first circuit,
• wherein said first circuit is operative by a first voltage,
• wherein said second circuit is operative by the first voltage and a second voltage which is smaller than the first voltage,
• wherein said second circuit includes:
• a static memory cell;
• a word line and a data line each coupled to the static memory cell;
• a peripheral circuit coupled to the word line and the data line, the second voltage being coupled to the peripheral circuit as a power supplier thereto;
• a power supply terminal to which the first voltage is applied;
• and
• a voltage generator to generate the second voltage on a basis of the first voltage,
• wherein a power supply voltage to be supplied to the static memory cell is larger than the second voltage, and
• wherein an internal supply voltage of the static memory cell is controlled in a state that the static memory cell is selected.

A semiconductor device comprising:

• a plurality of input/output terminals;
• a first circuit coupled to said plurality of input/output terminals;
• and
• a second circuit coupled to said first circuit,
• wherein said first circuit is operative by a first voltage,
• wherein said second circuit is operative by the first voltage and a second voltage which is smaller than the first voltage,
• wherein said second circuit includes:
• a static memory cell;
• a word line and a data line each coupled to the static memory cell;
• and
• a peripheral circuit coupled to the word line and the data line,
• wherein a power supply voltage to be supplied to the static memory cell is larger than the second voltage,
• wherein MOS transistors included in the static memory cell have gate insulators that are thinner than gate insulators of MOS transistors included in the peripheral circuit, and
• wherein an internal supply voltage of the static memory cell is controlled in a state that the static memory cell is selected.

A semiconductor device comprising:

• a plurality of input/output terminals;
• a first circuit coupled to said plurality of input/output terminals;
• and
• a second circuit coupled to said first circuit,
• wherein said first circuit is operative by a first voltage,
• wherein said second circuit is operative by the first voltage and a second voltage which is smaller than the first voltage,
• wherein said second circuit includes:
• a static memory cell;
• a word line and a data line each coupled to the static memory cell;
• and
• a switch coupled to a power supply node of the static memory cell,
• wherein a power supply voltage to be supplied to the static memory cell is larger than the second voltage,
• wherein the power supply node of the static memory cell is coupled to the first voltage by the switch,
• wherein the switch is made be in a state of non-conduction in case that the word line is made be in a state of selected, and
• wherein an internal supply voltage of the static memory cell is controlled in a state that the static memory cell is selected.

A semiconductor device comprising:

• a plurality of input/output terminals;
• a first circuit coupled to said plurality of input/output terminals;
• and
• a second circuit coupled to said first circuit,
• wherein said first circuit is operative by a first voltage,
• wherein said second circuit is operative by the first voltage and a second voltage which is smaller than the first voltage,
• wherein said second circuit includes:
• a static memory cell;
• and
• a word line and a data line each coupled to the static memory cell,
• wherein a power supply voltage to be supplied to the static memory cell is larger than the second voltage,
• wherein the static memory cell has a first inverter and a second inverter, an output of each one of the first and second inverters being coupled to an input of the other,
• wherein the second voltage is lower than a threshold voltage of each MOS transistor included in the first and second inverters, and
• wherein an internal supply voltage of the static memory cell is controlled in a state that the static memory cell is selected.