Asymmetrical Random Access Memory Cell, A Memory Comprising Asymmetrical Memory Cells And A Method To Operate Such A Memory

Abstract

Asymmetrical random access memory cell (1) comprising cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistor (21, 31), wherein the random access memory cell is asymmetrical by means of the cross coupled inverters (2, 3) which have asymmetrically physical behaviours whereby different switching thresholds of the inverters are present, and that the pass-transistors (21, 31) are driven by separate controlled wordlines (wl, wwl). Furthermore the invention relates to a random access memory comprising a plurality of such asymmetrical random access memory cells and to a method to operate such a random access memory.

Dependencies are inferred from the claim text.