High speed otp sensing scheme
AssigneeSidense Corp.
InventorsWlodek Kurjanowicz, Steven Smith
Life of this patent
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Abstract
A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.
Claims32
A memory array including one-time-programmable (OTP) memory cells, comprising
- a pair of complementary bitlines, each bitline of the pair of complementary bitlines being connected to diffusion terminals of the OTP memory cells;
- a precharge circuit for precharging the pair of complementary bitlines to a first voltage level;
- wordlines connected to gate terminals of the OTP memory cells, at least one wordline capable of driving one bitline of the pair of complementary bitlines to a second voltage level through a programmable conductive link of a corresponding OTP memory cell;
- and,
- a bitline sense amplifier for sensing a voltage differential on the pair of complementary bitlines.
A method for sensing one time programmable (OTP) memory cells connected to complementary bitlines, comprising:
- a) precharging a pair of complementary bitlines to a first voltage level, the pair of complementary bitlines including a data bitline and a reference bitline;
- b) driving at least one wordline to a second voltage level;
- c) charging the data bitline towards the second voltage with an OTP memory cell connected to the wordline if the OTP memory cell is programmed;
- and,
- d) sensing a voltage difference between the reference bitline and the data bitline.
A method for sensing one time programmable (OTP) memory cells connected to a pair of complementary bitlines, the pair of complementary bitlines including a data bitline and a reference bitline, the method comprising:
- a) coupling capacitance means to the data bitline, said capacitance means defining an offset of a sense amplifier;
- b) precharging the data bitline and the reference bitline to a first voltage level;
- c) driving a wordline to a second voltage level;
- d) charging the data bitline towards the second voltage level with an OTP memory cell connected to the wordline if the OTP memory cell is programmed, and,
- e) activating the sense amplifier to determine a voltage difference between the data bitline and the reference bitline.
A complementary bitline memory array comprising:
- one time programmable (OTP) memory cells connected to bitlines and wordlines;
- a first precharge circuit for selectively precharging a selected complementary bitline pair to a first voltage level;
- a second precharge circuit for selectively precharging bitlines adjacent to the selected complementary bitline pair to a second voltage level;
- and,
- a sense amplifier coupled to the selected complementary bitline pair through column select devices in response to decoded column address signals.
A method for precharging a complementary bitline memory array having one time programmable (OTP) memory cells, comprising:
- a) precharging selected bitline pairs to a first voltage level;
- b) precharging unselected bitlines adjacent to the selected bitline pairs to a second voltage level;
- c) driving at least one wordline connected to the OTP memory cells, the OTP memory cells being able to charge one bitline of each of the selected bitline pairs towards the wordline voltage level if the OTP memory cells are programmed, while the driving ability of the OTP memory cells connected to the bitlines precharged to the second voltage level is suppressed.
Dependencies are inferred from the claim text.