US 2007/0165436 A1 · High-speed and low-power differential non-volatile content addressable memory cell and array

Abstract

A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage. Finally, the second terminals of each storage element is connected to a second voltage, different from the first voltage. A current passing through the memory cell is indicative of a mis-match between the contents of the compare data lines and the contents of the storage elements.

Claims21

Dependent claims

1-14. (canceled)

A differential non-volatile content addressable memory cell comprising:

a pair of non-volatile storage elements each of said storage elements is characterized by capable of being in one of two non-volatile states:
a first state in which a first current flows through said storage element, and a second state in which a second current less than said first current flows through said storage element;
a match line;
a volatile storage element capable of storing said first state and said second state;
said volatile storage element having a first output and a second output;
said first and second outputs for controlling the flow of current from said match line;
and
a pair of differential data lines;
each for supplying data to one of said non-volatile storage elements, and for transferring the data from said pair of non-volatile storage elements to said volatile storage element;
and for controlling the flow of current from said match line.

7 more elements

A differential non-volatile content addressable memory array comprising:

a plurality of cells arranged in a plurality of rows and columns;
each cell comprising:
a pair of non-volatile storage elements each of said storage elements is characterized by capable of being in one of two non-volatile states:
a first state in which a first current flows through said storage element, and a second state in which a second current less than said first current flows through said storage element;
a match line connecting cells arranged in the same row;
a volatile storage element capable of storing said first state and said second state;
said volatile storage element having a first output and a second output;
said first and second outputs for controlling the flow of current from said match line;
and
a pair of differential data lines connecting cells in the same column, each data line for supplying data to one of said non-volatile storage elements, and for transferring the data from said pair of non-volatile storage elements to said volatile storage element;
and for controlling the flow of current from said match line.

8 more elements

Dependencies are inferred from the claim text.

High-speed and low-power differential non-volatile content addressable memory cell and array

Life of this patent

High-speed and low-power differential non-volatile content addressable memory cell and array

Life of this patent

Abstract

Claims21