Interconnection pattern design

A semiconductor component comprising a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the interconnection pattern has substantially rounded or chamfered corners, wherein the interconnection pattern comprises a plurality of first interconnections, which first interconnections are electrically connecting, and a plurality of second interconnections, which second interconnections are electrically non-connecting, wherein the second interconnections are on the periphery of the interconnection pattern, and wherein the second interconnections are relatively weaker than the first interconnections.

A semiconductor component comprising a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the interconnection pattern has substantially rounded or chamfered corners, wherein the interconnection pattern comprises a plurality of first interconnections, which first interconnections are electrically connecting, and a plurality of second interconnections, which second interconnections are electrically non-connecting, wherein the second interconnections form one or more angular or rectangular corners of the interconnection pattern, and wherein the second interconnections are relatively weaker than the first interconnections.

A semiconductor device comprising at least one printed wiring board (PWB) and at least one semiconductor component bonded to the PWB, wherein interconnections formed as an interconnection pattern between the PWB and at least one semiconductor component are aligned such that the interconnection pattern has substantially rounded or chamfered corners, wherein the interconnection pattern comprises a first plurality of interconnections, which first interconnections are electrically connecting, and a second plurality of interconnections, which second interconnections are electrically non-connecting, on the periphery of the interconnection pattern and/or forming one or more angular or rectangular corners of the interconnection pattern, wherein the second interconnections are relatively weaker than the first interconnections.

A semiconductor device comprising at least one printed wiring board (PWB) and at least one semiconductor component bonded to the PWB, wherein interconnections formed as an interconnection pattern between the PWB and at least one semiconductor component are aligned such that the interconnection pattern has substantially rounded or chamfered corners, wherein the interconnection pattern comprises a plurality of first interconnections, which first interconnections are electrically connecting, and a plurality of second interconnections, which second interconnections are electrically non-connecting, wherein the second interconnections are on the periphery of the interconnection pattern, and wherein the second interconnections are relatively weaker than the first interconnections.

A semiconductor device comprising at least one printed wiring board (PWB) and at least one semiconductor component bonded to the PWB, wherein interconnections formed as an interconnection pattern between the PWB and at least one semiconductor component are aligned such that the interconnection pattern has substantially rounded or chamfered corners, wherein the interconnection pattern comprises a plurality of first interconnections, which first interconnections are electrically connecting, and a plurality of second interconnections, which second interconnections are electrically non-connecting, wherein the second interconnections form one or more angular or rectangular corners of the interconnection pattern, and wherein the second interconnections are relatively weaker than the first interconnections.