Esd test arrangement and method

A program-controlled arrangement for the identification of ESD and/or latch-up weak points in a design or in a concept of an integrated circuit, the arrangement comprising:

• a pre-processor, configured to process data about a description of the integrated circuit and about ESD-characterized circuit parts of the integrated circuit and information about ESD test standards, in order to create an abstracted network list for the ESD simulation, the abstracted network list having less data than is required for a complete depiction of the integrated circuit;
• a simulator device operably connected to receive the abstracted network list from the pre-processor, the simulator device having a simulator configured to perform an ESD simulation of the integrated circuit using the abstracted network list, the simulator device having a monitoring controller configured to control an ESD simulation sequence in the simulator;
• and
• an analysis device operably connected to the simulator device, the analysis device operable to perform an evaluation of data generated in the simulator device with regard to physical validity and meaningfulness and to mark simulation runs having physically relevant ESD failure events.

A method for the identification of ESD and/or latch-up weak points in the design or in the concept of an integrated circuit, comprising:

• a) using a pre-processor to process data about a description of the integrated circuit and about ESD-characterized circuit parts of the integrated circuit and information about ESD test standards, in order to create an abstracted network list for the ESD simulation, the abstracted network list having less data than is required for a complete depiction of the integrated circuit;
• b) employing a simulator device to perform an ESD simulation of the integrated circuit, and to control the ESD simulation sequence in the simulator;
• and
• c) employing an analysis device to perform an evaluation of data generated in the simulator device with regard to physical validity and meaningfulness and to mark the simulation runs having physically relevant ESD failure events.

A method for the identification of ESD and/or latch-up weak points in the design or in the concept of an integrated circuit, comprising:

• a) using a pre-processor to process data about a description of the integrated circuit and about ESD-characterized circuit parts of the integrated circuit and information about ESD test standards, in order to create an abstracted network list for the ESD simulation, the abstracted network list having less data than is required for a complete depiction of the integrated circuit;
• b) employing a simulator device to perform an ESD simulation of the integrated circuit using a simulation path having a first simulator and a second simulator operably coupled to the first simulator, and to control the ESD simulation sequence in the simulator device;
• and
• c) employing an analysis device to perform an evaluation of data generated in the simulator device with regard to physical validity and meaningfulness and to mark the simulation runs having physically relevant ESD failure events.