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US 2007/0165318 A1Published application
Testing storage system electronics using loopback
AssigneeMarvell International Ltd.
InventorPantas Sutardja
Life of this patent
Estimating the term…
Abstract
A system includes a hard disk controller (HDC) module that controls a hard disk and a read channel (RC) device that communicates with the HDC module via a read bus and a write bus. The RC device includes a loopback circuit that selectively loops back the write bus to the read bus. The RC device generates a write clock for the HDC module to write data on the write bus and a read clock for the HDC module to read the data on the read bus, wherein the write clock is independent of the read clock.
Claims31
A system, comprising:
- a hard disk controller (HDC) module that controls a hard disk;
- and
- a read channel (RC) device that communicates with said HDC module via a read bus and a write bus, that includes a loopback circuit that selectively loops back said write bus to said read bus, that generates a write clock for said HDC module to write data on said write bus, and that generates a read clock for said HDC module to read said data on said read bus, wherein said write clock is independent of said read clock.
A system, comprising:
- a hard disk controller (HDC) module that controls a hard disk using a read bus and a write bus;
- a first-in first-out (FIFO) memory that buffers data on said read bus;
- and
- a read channel (RC) device that communicates with said HDC module via said read bus and said write bus, that includes a loopback circuit that selectively loops back said write bus to said read bus, and that generates a loopback clock that clocks said FIFO memory when said write bus is looped back to said read bus.
1 more element
A method, comprising:
- selectively looping back a write bus to a read bus between a hard disk controller (HDC) module and a read channel (RC) device in a disk drive;
- generating a write clock for said HDC module to write data on said write bus;
- and
- generating a read clock for said HDC module to read said data on said read bus, wherein said write clock is independent of said read clock.
1 more element
A method, comprising:
- selectively looping back a write bus to a read bus between a hard disk controller (HDC) module and a read channel (RC) device in a disk drive;
- buffering data on said read bus using a first-in first-out (FIFO) memory;
- and
- generating a loopback clock for clocking said FIFO memory when said write bus is looped back to said read bus.
1 more element
Dependencies are inferred from the claim text.