Liquid crystal display
OwnerHyeong-Jun Park, Chung-Hun Ha +1inventors
InventorsHyeong-Jun Park, Chung-Hun Ha, Hyang-Shik Kong
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Abstract
A liquid crystal display includes a gate line (formed on an insulating substrate) including a gate electrode, a gate insulation layer formed on the gate line, a semiconductor layer formed on the gate insulation layer., and a data line and a drain electrode formed on the semiconductor layer (stripe). A borderline (side edge) of the semiconductor layer (stripe) is positioned at the outside of a borderline (side edge) of the data line. In this way, by minimizing the overlap of the data line and the pixel electrode (so that a width of the data line is smaller than that of the semiconductor layer (stripe), parasitic capacitance is reduced, so that vertical line blur can be prevented.
Claims19
A liquid crystal display comprising an upper panel and a lower panel, the lower panel comprising:
- a gate line including a gate electrode formed on an insulating substrate;
- a gate insulation layer formed on the gate line;
- a semiconductor stripe formed on the gate insulation layer;
- and
- a data line formed on the semiconductor stripe,
- wherein the width of the semiconductor stripe is greater than the width of the data line.
A liquid crystal display comprising an upper panel and a lower panel, the lower panel comprising:
- a gate line including a chamfered gate electrode formed on an insulating substrate;
- a gate insulation layer formed on the gate line;
- a semiconductor layer formed on the gate insulation layer;
- and
- a data line, including a source electrode formed on the semiconductor layer;
- a drain electrode formed on the semiconductor layer, including a first portion of the drain electrode surrounded by the source electrode and having a width (d2), and including a second portion of the drain electrode not surrounded by the source electrode and having a width (d1), wherein (d1) is greater than width (d2),
A liquid crystal display, comprising an upper panel and a lower panel, the lower panel comprising:
- a gate line including a gate electrode formed on an insulating substrate;
- a gate insulation layer formed on the gate line;
- a semiconductor layer formed on the gate insulation layer;
- a data line formed on the semiconductor layer;
- a drain electrode formed on the semiconductor layer;
- a first passivation layer formed on the data line and on the drain electrode;
- a color filter formed on the first passivation layer;
- a pixel electrode formed on the color filter.
Dependencies are inferred from the claim text.