Back to results
US 2007/0165041 A1Published application
Method and apparatus of reporting memory bit correction
AssigneeIntel Corporation
InventorsTsvika Kurts, Moty Mehalel, Julius Mandelblat, Alexander Gendler
Life of this patent
Estimating the term…
Abstract
Briefly, a method, main processing unit and a computer system to report a failure in a bit of a memory line by updating first and second counters for a first time and a second time correction of bit failures in a line, respectively. The updating of first and second counters after a third time correction of bit failure in the line is disabled.
Claims29
A method comprising:
- updating first and second counters for a first time and a second time correction of bit failure in a line, respectively;
- and
- disabling un update of the first and second counters after a third time correction of bit failure in the line.
A memory comprising:
- two or more lines, wherein a line includes a plurality of data bits and first and second status bits to report a correction of failure in data bits of the line.
The memory of claim 7, wherein the first status bit is updated for a first failure of a bit of the line.
A main processing unit comprising:
- a memory having two or more lines, wherein a line includes a plurality of data bits and first and second status bits to report a correction of failure in data bits of the line;
- and
- a report register to report a number of corrections of the line according to the first and second status bits.
A computer system comprising:
- wireless network interface card to provide a connection to a network;
- and
- a main processing unit including:
- a memory having two or more lines, wherein a line includes a plurality of data bits and first and second status bits to report a correction of failure in data bits of the line;
- and
- a report register to report a number of corrections of the line according to the first and second status bits.
3 more elements
An article comprising:
- a storage medium having stored thereon instructions that when executed result in:
- updating first and second counters for a first time and a second time correction of bit failure in a line, respectively;
- and
- disabling un update of the first and second counters after a third time correction of bit failure in the line.
1 more element
Dependencies are inferred from the claim text.