Shift register and image display apparatus containing the same

An image display apparatus comprising a gate-line driving circuit formed of a plurality of shift registers connected in cascade, wherein

• each of said plurality of shift registers includes:
• a clock terminal and an output terminal;
• a first transistor connected between said output terminal and said clock terminal;
• a second transistor configured to discharge said output terminal;
• and
• a first pull-down driving circuit in which a first node to which a control electrode of said first transistor is connected serves as an input terminal and a second node to which a control electrode of said second transistor is connected serves as an output terminal, wherein
• said first pull-down driving circuit includes:
• third and fourth transistors connected in series between said second node and a first power terminal;
• a fifth transistor connected between said second node and a second power terminal;
• and
• a sixth transistor controlled to be at a potential at said second node to flow a feedback current to a third node serving as a connection node between said third and fourth transistors.

A shift register comprising:

• a clock terminal and an output terminal;
• a first transistor connected between said output terminal and said clock terminal;
• a second transistor configured to discharge said output terminal;
• an input terminal to which a signal defining timing of charging a first node to which a control electrode of said first transistor is connected;
• and
• a pull-down driving circuit in which said input terminal serves as an input terminal and a second node to which a control electrode of said second transistor is connected serves as an output terminal, wherein
• said pull-down driving circuit includes:
• third and fourth transistors connected in series between said second node and a first power terminal;
• a fifth transistor connected between said second node and a second power terminal;
• and
• a sixth transistor controlled to be at a potential at said second node to flow a feedback current to a third node serving as a connection node between said third and fourth transistors.

An image display apparatus comprising a gate-line driving circuit formed of a plurality of shift registers connected in cascade, wherein

• each of said plurality of shift registers includes:
• a clock terminal and an output terminal;
• a first transistor connected between said output terminal and said clock terminal;
• a second transistor configured to discharge said output terminal;
• an input terminal to which a signal defining timing of charging a first node to which a control electrode of said first transistor is connected;
• and
• a pull-down driving circuit in which a first node to which a control electrode of said first transistor is connected serves as an input terminal and a second node to which a control electrode of said second transistor is connected serves as an output terminal, wherein
• said pull-down driving circuit includes:
• third and fourth transistors connected in series between said second node and a first power terminal;
• a fifth transistor connected between said second node and a second power terminal;
• and
• a sixth transistor controlled to be at a potential at said second node to flow a feedback current to a third node serving as a connection node between said third and fourth transistors.