Pipelined analog-to-digital converters
AssigneeMarvell World Trade Ltd.
InventorSehat Sutardja
Life of this patent
Estimating the term…
Abstract
A pipelined analog to digital converter comprises a first ADC stage that receives one of an input voltage and a first residue voltage and a first voltage reference and that generates a first digital signal and a second residue voltage. A second ADC stage receives the second residue voltage from the first ADC stage and a second voltage reference and that generates a second digital signal, wherein the second voltage reference is lower than the first voltage reference.
Claims32
A pipelined analog to digital converter (ADC), comprising:
- a first ADC stage that receives one of an input voltage and a first residue voltage, that receives a first voltage reference, and that generates a first digital signal and a second residue voltage;
- and
- a second ADC stage that receives said second residue voltage and a second voltage reference and that generates a second digital signal,
- wherein said second voltage reference is lower than said first voltage reference, and wherein at least one of said first voltage reference and said second voltage reference is a digital reference.
A pipelined analog to digital converter (ADC), comprising:
- first ADC stage means for receiving one of an input voltage and a first residue voltage, for receiving a first voltage reference, and for generating a first digital signal and a second residue voltage;
- and
- second ADC stage means for receiving said second residue voltage and a second voltage reference and for generating a second digital signal,
- wherein said second voltage reference is lower than said first voltage reference, and wherein said second voltage reference is independent of said first voltage reference.
A method for operating a pipelined analog to digital converter, comprising:
- receiving one of an input voltage and a first residue voltage at a first ADC stage;
- receiving a first voltage reference at said first ADC stage;
- generating a first digital signal and a second residue voltage;
- receiving said second residue voltage from said first ADC stage and a second voltage reference at a second ADC stage;
- generating a second digital signal, wherein said second voltage reference is lower than said first voltage reference;
- and
- receiving a third voltage reference at a third ADC stage that is lower than said second voltage reference.
Dependencies are inferred from the claim text.