US 2007/0164887 A1 · PROGRAMMABLE REFERENCE VOLTAGE GENERATOR

Abstract

A reference generator circuit has a resistor string between the potentials of the power supply voltage that is partitioned into a top string, a middle string, and a bottom string. PFET devices are used to couple the positive power supply voltage a selected node of the top string in response to first control signals and complementary second control signals are used to control NFET devices that couple the ground power supply voltage to a selected node of the bottom string. If a resistor is effectively removed from the top string a corresponding resistor is effectively added in the bottom string keeping the total resistance in the resistor string substantially constant. A pass gate network is used to select between nodes of the middle string as a vernier for generating small step sizes.

Claims20

Dependent claims

A reference generator for generating a programmable reference voltage comprising:

a series connection of a number N resistors forming N+1 nodes;
a plurality of first electronic switches each configured to couple a first voltage potential to a selected first node of the N+1 nodes in response to a corresponding one of a plurality of first control signals;
a plurality of second electronic switches each configured to couple a second voltage potential to a selected second node of the N+1 nodes in response to a corresponding one of a plurality of second control signals;
and
an output coupled to one of the N+1 nodes between the selected first node and the selected second node thereby generating the programmable reference voltage at the output, wherein a resistance between the selected first node and selected second node remains substantially a constant value when the programmable reference voltage at the output is varied in response to the first and second control signals.

2 more elements

A data processing system comprising:

a central processing unit (CPU);
a random access memory (RAM);
an input output (I/O) interface unit;
and
a bus for coupling the CPU, RAM and I/O interface unit, the data processing system having circuitry for pseudo differential signaling including a programmable reference voltage generator having a series connection of a number N resistors forming N+1 nodes, a plurality of first electronic switches each configured to couple a first voltage potential to a selected first node of the N+1 nodes in response to a corresponding one of a plurality of first control signals, a plurality of second electronic switches each configured to couple a second voltage potential to a selected second node of the N+1 nodes in response to a corresponding one of a plurality of second control signals, and an output coupled to one of the N+1 nodes between the selected first node and the selected second node thereby generating the programmable reference voltage at the output, wherein a resistance between the selected first node and selected second node remains substantially a constant value when the programmable reference voltage at the output is varied in response to the first and second control signals.

2 more elements

Dependencies are inferred from the claim text.

Programmable reference voltage generator

Life of this patent

Programmable reference voltage generator

Life of this patent

Abstract

Claims20