Clock pulse generator apparatus with reduced jitter clock phase

Apparatus for converting between analogue and digital signals comprising:

• continuous-time sigma-delta conversion means;
• and
• clock pulse generator apparatus comprising a clock pulse generator for generating a train of return-to zero primary clock pulses each having leading and trailing edges defining alternately an active clock phase and a non-active clock phase;
• delay means for producing a train of delayed clock pulses presenting delayed edges whose timing relative to corresponding edges of said primary clock pulses is defined by said delay means, and
• combining means for producing a train of combined clock pulses presenting leading and trailing edges defined alternately by one of said delayed edges and the corresponding edge of the primary clock pulse, so that the active clock phases of said combined clock pulses have widths defined by said delay means, the variability of said widths of said active clock phases being smaller than the variability of the positions of said leading and trailing edges of said primary clock pulses, and the widths of said non-active clock phases varying as a function of variation in the positions of said primary clock pulses.