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US 2007/0164829 A1Published application
Sigma-delta fractional-N PLL with reduced frequency error
AssigneeSamsung Electronics Co., Ltd.
InventorSang-Soo Ko
Life of this patent
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Abstract
A sigma-delta fractional-N phase locked loop has faster lock time with increased charge pump current and decreased loop filter resistance in the unlock state. On the other hand, the sigma-delta fractional-N phase locked loop has lower noise susceptibility and lower frequency error with gradual decrease in charge pump current and gradual increase in loop filter resistance, in the lock state.
Claims20
A sigma-delta fractional-N phase locked loop, comprising:
- a controller for generating at least one control signal indicating a lock state or an unlock state of the phase locked loop;
- and
- a loop filter that successively increases a resistance therein through at least one intermediate resistance from a low resistance to a high resistance when the at least one control signal indicates the lock state.
A method of operating in a lock state within a sigma-delta fractional-N phase locked loop, comprising:
- generating at least one control signal indicating the lock state or an unlock state of the phase locked loop;
- and
- successively increasing a resistance in a loop filter of the phase locked loop through at least one intermediate resistance from a low resistance to a high resistance when the at least one control signal indicates the lock state.
Dependencies are inferred from the claim text.