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US 2007/0164815 A1Published application
Power amplifier circuit reducing electromagnetic interference
AssigneeSamsung Electronics Co., Ltd.
InventorJong-Haeng Lee
Life of this patent
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Abstract
A power amplifier circuit including a power transistor unit generating an output signal based on a predetermined pulse-width modulated signal. The power transistor unit includes a plurality of transistors and a delay circuit unit. The delay circuit unit sequentially drives the plurality of transistors with a predetermined time delay based on the pulse-width modulated signal.
Claims14
A power amplifier circuit comprising a power transistor unit generating an output signal based on a predetermined pulse-width modulated signal,
- wherein the power transistor unit comprises:
- a plurality of transistors;
- and
- a delay circuit unit sequentially driving the plurality of transistors with a predetermined time delay based on the pulse-width modulated signal.
1 more element
A class-D power amplifier circuit comprising:
- a plurality of first group transistors sequentially turned on or off according to a PMOS input signal based on a predetermined pulse-width modulated signal;
- and
- a plurality of second group transistors sequentially turned on or off according to an NMOS input signal based on the predetermined pulse-width modulated signal.
A class-D power amplifier circuit comprising:
- an input gain stage unit receiving a predetermined signal and generating a first input signal and a second input signal;
- a pulse width modulation (PWM) unit performing PWM on the first input signal to generate first, second, third, and fourth pulse-width modulated signals;
- a first power transistor unit comprising a plurality of first group transistors sequentially turned on or off according to the first pulse-width modulated signal and a plurality of second group transistors sequentially turned on or off according to the second pulse-width modulated signal, the first power transistor unit generating a first output signal;
- and
- a second power transistor unit comprising a plurality of third group transistors sequentially turned on or off according to the third pulse-width modulated signal and a plurality of fourth group transistors sequentially turned on or off according to the fourth pulse-width modulated signal, the second power transistor unit generating a second output signal.
2 more elements
Dependencies are inferred from the claim text.