High voltage tolerant bias circuit with low voltage transistors
AssigneeCypress Semiconductor Corporation
InventorsT.V. Chanakya Rao, Badrinarayanan Kothandaraman
Life of this patent
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Abstract
A circuit (200) can include a bias protection circuit (204) and a reference circuit (202). A bias protection circuit (204) can generate an internal power supply voltage (Vsuppi) from a higher device power supply (Vcch) with low voltage transistors and no resistors. A lower internal power supply voltage (Vsuppi) can be provided by buffer transistors (M5 and M6) that are biased according to limit section (206) that generates a bias voltage (biasn2) based on a threshold voltage drop and a feedback bias voltage (biasn1) from reference circuit (202).
Claims20
A voltage bias circuit, comprising:
- a self-biased reference circuit disposed between an internal power supply node and a reference node and comprising bias circuits that provide at least one reference value based on a stable bias potential at least one internal node;
- and
- a bias protection circuit coupled between a device power supply node and the reference node, the bias protection circuit comprising
- a drive circuit that enables a controllable impedance path between the device power supply node and the internal power supply node according to a potential at least a first supply bias voltage node, and
- a limit circuit that enables a first current path between the first supply bias voltage node and the reference node when the first supply bias voltage node exceeds a first predetermined limit with respect to the potential at the reference node.
A method of generating references voltages with a high voltage power supply and low voltage transistors, comprising the steps of:
- establishing a first supply bias voltage with at least one series of diode connected transistors coupled to a reference voltage node and a first current supply transistor biased according to a reference bias voltage;
- biasing a first supply transistor coupled to a device power supply node according to the first supply bias voltage to generate an internal power supply voltage less than the device power supply voltage;
- and
- powering a self-bias reference circuit with the internal power supply voltage to generate the reference bias voltage at a level between the internal power supply voltage and the reference node.
Dependencies are inferred from the claim text.