Regulator circuit

A regulator circuit, having a voltage output terminal, the regulator circuit comprising:

• a voltage source module, used for providing a driving voltage;
• a current mirror module, receiving the driving voltage and comprising a first current terminal, a second current terminal, and a third current terminal, wherein the first current terminal is coupled to a driving current, and the driving current is copied to the second and the third current terminals;
• an output module, being coupled to the voltage output terminal and generating a first control voltage and a second control voltage according to the voltage level of the voltage output terminal;
• a first PMOS transistor, the source of the first PMOS transistor being coupled to the second current terminal, the drain of the first PMOS transistor being grounded, and the gate of the first PMOS transistor receiving the first control voltage;
• a second PMOS transistor, the source of the second PMOS transistor being coupled to the third current terminal, the drain of the second PMOS transistor being grounded, and the gate of the second PMOS transistor being coupled to the source of the first PMOS transistor;
• and
• a third PMOS transistor, the source of the third PMOS transistor receiving the driving voltage, the gate of the third PMOS transistor being coupled to the third current terminal, and the drain of the third PMOS transistor being coupled to the output module and the voltage output terminal.

A regulator circuit, having a voltage output terminal, the regulator circuit comprising:

• a voltage source module, used for providing a driving voltage;
• a current mirror module, receiving the driving voltage and having a current input terminal, a second current terminal, and a third current terminal, wherein the current input terminal receives a driving current, and the driving current is copied to the second and the third current terminals;
• an output module, being coupled to the voltage output terminal, generating a first control voltage and a second control voltage according to the voltage level of the voltage output terminal;
• a first NMOS transistor, the drain of the first NMOS transistor being coupled to a common voltage, the gate of the first NMOS transistor receiving the first control voltage, and the source of the first NMOS transistor being coupled to the second current terminal;
• a second NMOS transistor, the drain of the second NMOS transistor being coupled to the common voltage, the source of the second NMOS transistor being coupled to the third current terminal, and the gate of the second NMOS transistor being coupled to the source of the first NMOS transistor and to the second current terminal;
• and
• a third NMOS transistor, the source of the third NMOS transistor receiving the driving voltage, the gate of the third NMOS transistor being coupled to the third current terminal, and the drain of the third NMOS transistor being coupled to the output module and the voltage output terminal.