Pull-up circuit for an input buffer
AssigneeCypress Semiconductor Corporation
InventorsPulkit Shah, Prasad Kotra
Life of this patent
Estimating the term…
Abstract
An input buffer has a high voltage leg in parallel with a low voltage leg. The low voltage leg pulls up the pad when the pad voltage is below the power supply voltage. The high voltage leg remains off when the pad voltage is below the power supply. The low voltage leg is turned off when the pad voltage is above the power supply voltage. The high voltage leg is on when the pad voltage is above power supply voltage. A low voltage bias circuit and a high voltage bias circuit protect the transistors in the low and voltage legs when the pad voltage is above the power supply voltage. As a result, the pull-up circuit is high voltage tolerant and does not sink the current from pad.
Claims20
A pull-up circuit for an input buffer, comprising:
- a pad;
- a first pmos transistor having a source and a drain;
- a second pmos transistor having a source and a drain, wherein the first and second pmos transistors are coupled in series, and the drain of the second pmos transistor is coupled to the pad;
- a first node coupled to substrates of the first pmos transistor and the second pmos transistor;
- and
- a power supply coupled to the source of the first pmos transistor.
A pull-up circuit for an input buffer, comprising:
- a pmos transistor having a drain
- a pad electrically coupled to the drain of the pmos transistor;
- and
- a resistor electrically coupled to the drain of the pmos transistor.
A pull-up circuit for an input buffer, comprising:
- a pad;
- a high voltage pull-up leg having a node coupled to the pad;
- a low voltage pull-up leg electrically in parallel with the high voltage pull-up leg.
Dependencies are inferred from the claim text.