Data recovery system for source synchronous data channels

An analog differential deskew circuit for reducing a time skew (deskewing) of two polarities of a differential signal, comprising:

• a number of analog delay units arranged sequentially;
• a means for selecting a composite delay resulting from selected analog delay units;
• and
• a means for inserting the composite delay into the polarities of the differential signal to reduce the time skew.

A method of deskewing a differential signal having two polarities, comprising the steps of:

• forming a variable analog delay comprising a number of analog delay units arranged sequentially;
• selecting a composite delay resulting from selected analog delay units;
• and
• inserting the composite delay into the polarities of the differential signal to reduce the time skew.

An analog front end (AFE) circuitry for reducing distortion of a differential data signal, comprising an analog differential deskew circuit for adjusting a time skew of two polarities of the differential data signal, the differential deskew circuit comprising:

• one or more analog delay units arranged sequentially;
• an analog selector, selecting a composite delay resulting from the delay units selected by the analog selector;
• and
• analog switches, inserting the composite delay into the polarities of the differential signal.

A system for reducing a time skew between two polarities of a differential signal representing a digital bit stream comprising:

• (a) a variable analog delay for inserting a variable time delay into polarities of the differential signal for generating a deskewed signal;
• (b) a multi-phase clock for generating a number M of clock phases per bit of the digital bit stream for oversampling the deskewed signal into a digital representation of the deskewed signal;
• (c) a logic circuit for estimating the quality of the digital representation of the deskewed signal;
• and
• (d) a means for adjusting the variable analog delay in response to the estimated quality of the digital representation of the deskewed signal to improve said quality.

A method for reducing a time skew between two polarities of a differential signal representing a digital bit stream, comprising the steps of:

• (a) generating a deskewed signal by inserting a variable analog delay into polarities of the differential signal;
• (b) generating a multi-phase clock signal having at least M phases per bit of the digital bit stream;
• (c) oversampling the deskewed signal with the multi-phase clock into a digital representation of the deskewed signal;
• (d) estimating the quality of the digital representation of the deskewed signal;
• and
• (e) adjusting the variable analog delay in response to the estimated quality of the digital representation of the deskewed signal to improve said quality.