Delay locked loop with selectable delay
AssigneeHoneywell International Inc.
InventorJon Josephson
Life of this patent
Estimating the term…
Abstract
A DLL includes a control module coupled with a phase detect signal. The phase detect signal is used by a control module to generate feedback and output select signals. The feedback and output select signals are each coupled to a multiplexer. Each multiplexer is coupled to a Multi-Tap Delay Line (MTDL). The MTDL provides a plurality of delayed signals that are selectable by the two multiplexers. The first multiplexer, coupled to the feedback select signal, selects a feedback clock signal. The second multiplexer, coupled to the output select signal, select a DLL output signal. The control module may receive other signals, such as a delay select signal, that may be used to program or set the delay of the output signal. In addition, a plurality of output signals may be available from the DLL.
Claims23
A Delay Locked Loop (DLL), comprising:
- a control module coupled to receive a phase detect signal, the control module deriving a feedback select signal and an output select signal based on the phase detect signal;
- a Multi-Tap Delay Line (MTDL) coupled to receive a reference clock signal, the MTDL comprising a plurality of delay taps, each delay tap outputting a delayed reference clock signal, the MTDL, thereby, providing a plurality of delayed reference clock signals;
- a first multiplexer coupled to receive the feedback select signal and the plurality of delayed reference clock signals, the first multiplexer selecting, via the feedback select signal, a first delayed reference clock signal from the plurality of delayed reference clock signals as a feedback clock signal;
- and
- a second multiplexer coupled to receive the output select signal and the plurality of delayed reference clock signals, the second multiplexer selecting, via the output select signal, a second delayed reference clock signal from the plurality of delayed reference clock signals as a first output signal.
A method of delaying a signal with a Delay Locked Loop (DLL), the method comprising:
- providing a phase detect signal to a control module, wherein the phase detect signal represents a measure of a phase difference between a reference clock signal and a feedback clock signal;
- deriving, via the control module, an offset select signal and an output select signal;
- providing the reference clock signal to a delay line, the delay line providing a plurality of signal taps, each signal tap providing a distinct delay time, the delay line, thereby, providing a plurality of selectable reference signals;
- providing the feedback select signal to a first multiplexer and the output select signal to a second multiplexer;
- with the first multiplexer, selecting, via the feedback select signal, a first selected reference signal from the plurality of selectable reference signals, the first multiplexer outputting the first selected reference signal as the feedback clock signal;
- and
- with the second multiplexer, selecting, via the output select signal, a second selected reference signal from the plurality of selectable reference signals, the second multiplexer outputting the second selected reference signal as an output signal of the DLL.
A method of delaying a signal within a Delay Locked Loop (DLL), the method comprising:
- deriving first and second feedback signals from a reference signal, the first and second feedback signals having different phases;
- and
- coupling the first and second feedback signals with a logic circuit, the logic circuit producing an output signal based on mathematical operations performed with the first and second feedback signals by the logic circuit, wherein a multiplexer is coupled to receive the output signal at a select input, the multiplexer selecting, via the output select signal, a delay of the reference signal.
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Dependencies are inferred from the claim text.