Method and apparatus to eliminate clock phase error in a multi-phase clock circuit

A method for generating multi-phase clock signals comprising:

• generating a master clock signal;
• applying the master clock signal to a delay-line;
• comparing a phase of an output signal of the delay-line with a phase of the master clock signal;
• and
• controlling at least one bias voltage of the delay line in response to the phase difference.

A method of eliminating clock phase error in a multi-phase clock, comprising:

• initiating a reference delay-per-stage control signal in a master signal control unit;
• applying a reference clock signal and the reference delay-per-stage control signal to a delay line;
• comparing a feedback signal generated by the delay line in response to the reference clock signal with the reference clock signal;
• generating a plurality of digital control codes related to the compared signals;
• and
• tuning the reference delay-per-stage in response to the digital control codes to accommodate clock phase error.

A multi-phase clocking system comprising:

• a memory controller including a master locked-loop signal generator structured to initiate a control signal;
• a first memory device including a first slave delay line structured to receive a first periodic signal and the control signal;
• and
• a second memory device including a second slave delay line structured to receive a second periodic signal and the control signal,
• wherein the first slave delay line and the second slave delay line each include:
• a phase detector for detecting a phase difference between the periodic signal and a respective delay line output signal generated in response to the periodic signal, and
• a bias control circuit for adjusting at least one bias voltage of the respective delay line in response to a signal related to the respective detected phase difference.