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US 2007/0164787 A1Published application
Method and apparatus for late timing transition detection
AssigneeIntel Corporation
InventorsEdward Grochowski, Chris Wilkerson, Shih-Lien Lu, Murali Annavaram
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Abstract
Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.
Claims21
An apparatus comprising:
- a first latch to hold a state of a data signal at a transition of a clock signal;
- a second latch to hold a state of the data signal at the transition of the clock signal;
- and
- comparison logic to compare an output of the first latch with an output of the second latch and to produce a first signal if the outputs are equal, and a second signal if the outputs are unequal.
1 more element
A method comprising:
- latching a data signal with a first set-up time relative to a clock signal edge;
- latching the data signal with a second set-up time relative to the clock signal edge;
- and
- comparing the first latched signal with the second latched signal to produce a comparison signal.
1 more element
A system comprising:
- a register;
- a detector;
- and
- an operational parameter adjustment mechanism;
- wherein
- the register is to store a data value relative to a clock signal edge;
- the detector is to signal a data value setup time shorter than a predetermined period relative to the clock signal edge;
- and
- the adjustment mechanism is to adjust a parameter of the system so that the detector signals a short set-up time in a predetermined ratio of clock signal periods.
6 more elements
Dependencies are inferred from the claim text.