Low-power fpga circuits and methods

An integrated circuit field programmable gate array (FPGA) containing an array of gates adapted for being programmed after manufacture for implementing desired electronic functionality, comprising:

• logic blocks configured for performing combinational or sequential logic operations based on programming of said FPGA in response to one or more logic inputs;
• said logic blocks configured for operating at a supply voltage Vdd selected from multiple discrete supply voltage levels;
• programmable routing channels configured for interconnecting said logic blocks for routing input signals to said logic blocks and output signals from said logic blocks based on programming of said FPGA;
• and
• memory cells within said FPGA for configuring logic block operation and signal routing within said programmable routing channels.

A method of placing and routing application logic within an FPGA fabric having multiple supply voltage levels, Vddx, levels, comprising:

• (a) receiving a net list;
• (b) assigning critical circuit paths defined within said net list to high supply voltage levels within the FPGA;
• (c) determining timing slack on non-critical circuit paths defined in said net list;
• (d) determining power sensitivity of circuit non-critical circuit paths;
• (e) assigning circuit paths with high power sensitivity and sufficient timing slack to logic blocks operating at a low supply voltage level;
• (f) updating timing information;
• (g) reversing assignment to logic blocks operating at a low supply voltage level if delay constraints are not met;
• and
• (h) continuing, iteratively, to execute steps (e) through (g) until all circuit paths within said net list have been assigned to blocks and routes within said FPGA.