US 2007/0164778 A1 · Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same

Abstract

A threshold detection circuit for developing a mode trigger signal includes an input that receives an input signal. In response to the input signal having approximately an input threshold value for a triggering time, the threshold detection circuit activates the mode trigger signal on an output. In response to the input signal being substantially different from the input threshold value or the input signal not having the input threshold value for the triggering time, the circuit deactivates the mode trigger signal. The threshold detection circuit may be contained in a variety of different mode detection circuits for detecting when an integrated circuit is to be placed in a test mode or other desired mode of operation, and such mode detection circuits may be contained in a variety of different types of integrated circuits, such as memory devices generally and SRAMs specifically.

Claims43

Dependent claims

1-64. (canceled)

A mode detection circuit, comprising:

an input circuit having an input and first and second outputs, the input circuit configured to generate a voltage differential between first and second outputs in response to receiving an input signal having a mode entry voltage sustained for a mode entry time;
and
an output circuit coupled to the first and second outputs and having a mode signal output, the output circuit configured to generate an active mode signal indicative of mode entry in response to detecting the voltage differential between the first and second outputs.

A mode detection circuit, comprising:

a mode-entry detection circuit having an input and an output, the input adapted to receive an input signal, the input signal having a first and second values when in a first mode, the mode-entry detection circuit operable to detect the input signal being approximately at a third value for a mode-entry time and correspondingly generate on the output a mode-entry signal indicative of entering a second mode, the third value being between the first and second values.

A mode detection circuit, comprising:

an input circuit configured to receive an input signal and to generate a first detection signal and a second detection signal responsive to the input signal, the input circuit further operable to generate the first detection signal at a first activation level and the second detection signal at a second activation level responsive to the received input signal having approximately a mode-entry value;
and
an output circuit coupled to the input circuit, the output circuit configured to receive the first and second detection signals, the output circuit operable to generate a mode-entry signal indicative of mode entry responsive to the first and second detection signals being at the first and second activation levels, respectively, for a mode-entry time.

A memory device, comprising:

an address bus;
a control bus;
a data bus;
an address decoder coupled to the address bus;
a control circuit coupled to the control bus;
a data access circuit coupled to the data bus;
a memory-cell array coupled to the address decoder, control circuit, and data access circuit, the memory-cell array having a plurality of memory cells arranged in rows and columns;
and
a mode detection circuit coupled to the memory-cell array, the mode detection circuit having an input and an output, the input adapted to receive an input signal having a first and second values when in a first mode, the mode detection circuit operable to generate on the output a mode-entry signal indicative of entering a second mode responsive to the received input signal being approximately at a third value for a mode-entry time.

6 more elements

A computer system, comprising:

a data input device;
a data output device;
a data storage device;
and
a computing circuitry coupled to the data input device, data output device, and data storage device, the computing circuitry having a memory device, the memory device comprising:
an address bus;
a control bus;
a data bus;
an address decoder coupled to the address bus;
a control circuit coupled to the control bus;
a data access circuit coupled to the data bus;
a memory-cell array coupled to the address decoder, control circuit, and data access circuit, the memory-cell array having a plurality of memory cells arranged in rows and columns;
and
a mode detection circuit coupled to the memory-cell array, the mode detection circuit having an input and an output, the input adapted to receive an input signal having a first and second values when in a first mode, the mode detection circuit operable to generate on the output a mode-entry signal indicative of entering a second mode responsive to the received input signal being approximately at a third value for a mode-entry time.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/726,478Filed 21 Mar 2007

Priority

1 Apr 2003

Published

19 Jul 2007

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 29/50004
Marginal testing, e.g. race, voltage or current testing: of threshold voltage
G01R 19/16557
Characterised by the application: logic probes, i.e. circuits indicating logic state
G01R 31/31701
Testing of digital circuits: arrangements for setting the Unit Under Test [UUT] in a test mode
G11C 29/46
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: test trigger logic

Family

Application10/405,328Continuation · filed 1 Apr 2003

Application11/433,219Division · filed 11 May 2006

Application11/433,219Continuation · filed 11 May 2006

Application11/726,478Division · filed 21 Mar 2007

US 2004/0199841 A1Published application

US 2006/0208758 A1Published application

US 7,183,792 B2Related patent

US 2007/0164778 A1This patent

From the US filing history. Foreign family members aren’t listed.

Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same

Life of this patent

Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same

Life of this patent

Abstract

Claims43