Method and apparatus for detection and prevention of bulk CMOS latchup
AssigneeInternational Business Machines Corporation
InventorDelbert Cecchi
Life of this patent
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Abstract
A method and apparatus are provided for detection and prevention of bulk complementary metal oxide semiconductor (CMOS) latchup. A separate power distribution is provided for coupling a positive voltage supply rail to the N well and a ground voltage supply rail to the P well of the CMOS circuit. At least one sensor monitors current flow in a bias voltage applied to at least one of an N well and a P well of the CMOS circuitry. A latchup event is detected responsive to a predefined increase in the monitored current flow. A switch temporarily interrupts the connection of at least one of the N well and the P well to the respective voltage supply rail when the latchup event is detected.
Claims15
Apparatus for detection and prevention of bulk CMOS latchup comprising:
- at least one sensor for monitoring current flow in a bias voltage applied to at least one of an N well and a P well of the CMOS circuitry;
- a latchup event being detected responsive to a predefined increase in the monitored current flow;
- at least one switch being coupled between a respective voltage supply rail and at least one of the N well and the P well of the CMOS circuitry and the CMOS circuitry voltage supply rail;
- a switch control coupled between said at least one sensor and said at least one switch for temporarily interrupting a connection of at least one of the N well and the P well and the CMOS circuitry voltage supply rail to voltage supply rail responsive to the latchup event being detected.
Apparatus for detection and prevention of bulk CMOS latchup comprising:
- a sensor for monitoring current flow in a bias voltage applied to an N well of the CMOS circuitry;
- a latchup event being detected responsive to a predefined increase in the monitored current flow;
- a separate power distribution for coupling a positive voltage supply rail to the N well of the CMOS circuitry and a ground voltage supply rail to the P well;
- and
- a switch for temporarily interrupting a connection of the N well and the CMOS circuitry positive voltage supply rail to the positive voltage supply rail responsive to the latchup event being detected.
A method for detecting and preventing latchup in a bulk CMOS circuit comprising the steps of:
- providing a separate power distribution for coupling a positive voltage supply rail to the N well of the CMOS circuit and a ground voltage supply rail to the P well of the CMOS circuit;
- monitoring current flow in a bias voltage applied to the N well of the CMOS circuit;
- detecting a latchup event responsive to a predefined increase in the monitored current flow;
- providing a switch coupled between the positive voltage supply rail and the N well and the CMOS circuit;
- applying a switch control signal to said switch for temporarily interrupting a connection of the N well and the CMOS circuit voltage supply rail to the voltage supply rail responsive to the latchup event being detected.
Dependencies are inferred from the claim text.