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US 2007/0164432 A1Published application
Semiconductor device having alignment post electrode and method of manufacturing the same
AssigneeCasio Computer Co., Ltd.
InventorsShinji Wakisaka, Tomohiro Ito, Shigeru Yokoyama, Osamu Kuwabara, Norihiko Kaneko, Syouichi Kotani
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Abstract
A semiconductor device includes a semiconductor substrate which has a plurality of semiconductor device formation regions and alignment mark formation region having the same planar size as that of the semiconductor device formation region, a plurality of post electrodes which are formed in each semiconductor device formation region, and an alignment post electrode which is formed in the alignment mark formation region and smaller in number than the post electrodes formed in each semiconductor device formation region.
Claims33
A semiconductor device comprising:
- a semiconductor substrate which has an upper surface including a plurality of semiconductor device formation regions and at least one alignment mark formation region having the same planar size as a planar size of each of the semiconductor device formation regions;
- a plurality of connection pads formed in each of the semiconductor device formation regions;
- an insulating film formed on the upper surface of the semiconductor substrate in all of the semiconductor device formation regions, including on the connection pads except for respective central portions thereof, and in the at least one alignment mark formation region;
- a plurality of post electrodes which are formed on an upper side of the insulating film in each of the semiconductor device formation regions and formed of metal, and each of which is electrically connected to at least a corresponding one of the connection pads;
- a temporary alignment post electrode formed of metal and a final alignment post electrode formed of the same material as the temporary alignment post electrode, which are formed on an upper side of the insulating film in the alignment mark formation region, and which are smaller in number than the post electrodes formed in each semiconductor device formation region, the final alignment post electrode having a planar size that is smaller than a planar size of the temporary alignment post electrode;
- and
- a sealing film which is made from an organic resin and which is formed between the post electrodes in each of the semiconductor device formation regions and on an outside of the temporary and final alignment post electrodes in the alignment mark formation region;
- wherein an upper surface of each of the temporary and final alignment post electrodes is exposed to outside and is flush with an upper surface of the sealing film.
5 more elements
A semiconductor device comprising:
- a semiconductor substrate which has an upper surface including a plurality of semiconductor device formation regions and at least one alignment mark formation region having the same planar size as a planar size of each of the semiconductor device formation regions;
- a plurality of connection pads formed in each of the semiconductor device formation regions;
- an insulating film formed on the upper surface of the semiconductor substrate in all of the semiconductor device formation regions, including on the connection pads except for respective central portions thereof, and in the at least one alignment mark formation region;
- a plurality of post electrodes which are formed on an upper side of the insulating film in each of the semiconductor device formation regions and each of which is electrically connected to at least a corresponding one of the connection pads;
- at least one alignment post electrode which is formed on an upper side of the insulating film in the alignment mark formation region, and which is smaller in number than the post electrodes formed in each semiconductor device formation region;
- and
- a sealing film which is made from an organic resin and which is formed between the post electrodes in each of the semiconductor device formation regions and on an outside of the alignment post in the alignment mark formation region;
- wherein an upper surface of the alignment post electrode is exposed to outside and is flush with an upper surface of the sealing film;
- and
- wherein the semiconductor substrate includes a plurality of non-semiconductor device formation regions around the alignment mark formation region, and each of the non-semiconductor device formation regions has the same planar size as the planar size of each of the semiconductor device formation regions and does not have post electrodes formed thereon.
7 more elements
A semiconductor device comprising:
- a semiconductor substrate which includes a plurality of semiconductor device formation regions and at least one alignment mark formation region having the same planar size as a planar size of each of the semiconductor device formation regions;
- a plurality of post electrodes which are formed in each of the semiconductor device formation regions;
- and
- at least one alignment post electrode which is formed in the alignment mark formation region, and which is smaller in number than the post electrodes formed in each of the semiconductor device formation regions;
- wherein the semiconductor substrate includes a plurality of non-semiconductor device formation regions around the alignment mark formation region, and each of the non-semiconductor device formation regions has the same planar size as the planar size of each of the semiconductor device formation regions and does not have post electrodes formed thereon.
2 more elements
A semiconductor device comprising:
- a semiconductor substrate which includes a plurality of semiconductor device formation regions and at least one alignment mark formation region having the same planar size as a planar size of each of the semiconductor device formation regions;
- a plurality of post electrodes which are formed in each of the semiconductor device formation regions and formed of metal;
- and
- a plurality of alignment post electrodes formed in the alignment mark formation region and formed of the same material as that of each of the post electrodes, and which are smaller in number than the post electrodes formed in each of the semiconductor device formation regions;
- wherein the alignment post electrodes include a plurality of kinds of alignment post electrodes having different planar shapes, including a temporary alignment post electrode for use in executing temporary alignment and a final alignment post electrode for use in executing final alignment, and wherein a planar area of the final alignment post electrode is smaller than a planar area of the temporary alignment post electrode.
2 more elements
A semiconductor device comprising:
- a semiconductor substrate which has an upper surface including a plurality of semiconductor device formation regions and at least one alignment mark formation region having the same planar size as a planar size of each of the semiconductor device formation regions;
- a plurality of connection pads formed in each of the semiconductor device formation regions;
- an insulating film formed on the upper surface of the semiconductor substrate in all of the semiconductor device formation regions, including on the connection pads except for respective central portions thereof, and in the at least one alignment mark formation region;
- a plurality of first and second metal films formed on the insulating film;
- a plurality of post electrodes which are respectively formed on the first metal films on the insulating film in each of the semiconductor device formation regions and each of which is electrically connected to at least a corresponding one of the connection pads;
- a plurality of alignment post electrodes which are formed on the second metal films on the insulating film in the alignment mark formation region, and which are smaller in number than the post electrodes formed in each semiconductor device formation region;
- a sealing film which is made from an organic resin and which is formed between the post electrodes in each of the semiconductor device formation regions and on an outside of the alignment post electrodes in the alignment mark formation region;
- wherein an upper surface of each of the alignment post electrodes is exposed to outside and is flush with an upper surface of the sealing film.
5 more elements
A semiconductor device comprising:
- a semiconductor substrate including a plurality of semiconductor device formation regions in each of which a plurality of connection pads are formed, and at least one alignment mark formation region having the same planar size as a planar size of each of the semiconductor device formation regions;
- a plurality of post electrodes which are formed in each of the semiconductor device formation regions and each of which is electrically connected to at least a corresponding one of the connection pads;
- and
- at least one alignment post electrode and at least one dummy electrode which are formed in the alignment mark formation region, the alignment post electrode being smaller in number than the post electrodes formed in each semiconductor device formation region, and the dummy electrode being not electrically connected to the connection pad.
1 more element
A method for manufacturing a semiconductor device, comprising:
- preparing a semiconductor substrate including a plurality of semiconductor device formation regions in each of which a plurality of connection pads are formed, and at least one alignment mark formation region having the same planar size as a planar size of each of the semiconductor device formation regions;
- and
- forming a plurality of post electrodes in each of the semiconductor device formation regions, each of the post electrodes being electrically connected to at least a corresponding one of the connection pads, and a plurality of dummy electrodes and at least one alignment post electrode in the alignment mark formation region, the alignment post electrode and the dummy post electrode being not electrically connected to the connection pad.
A method for manufacturing a semiconductor device, comprising:
- preparing a semiconductor substrate including a plurality of semiconductor device formation regions in each of which a plurality of connection pads are formed, and at least one alignment mark formation region having the same planar size as a planar size of each of the semiconductor device formation regions;
- forming a plurality of post electrodes in each of the semiconductor device formation regions, each of the post electrodes being electrically connected to at least a corresponding one of the connection pads, and at least one alignment post electrode in the alignment mark formation region, said at least one alignment post electrode includes at least one temporary post electrode and at least one final alignment post electrode;
- temporarily aligning the temporary post electrode on the silicon substrate for falling the final alignment post electrode within a camera including a low lens magnification;
- and
- finally aligning the final post electrode on the silicon substrate with an alignment mark in the camera including a high lens magnification.
2 more elements
Dependencies are inferred from the claim text.