Wafer level chip scale package having rerouting layer and method of manufacturing the same

A wafer level chip scale package comprising:

• a wafer arranged with bonding pads;
• a passivation layer formed on the wafer and exposing each of the bonding pads;
• a first interlayer insulating layer formed on the passivation layer, the first interlayer insulating layer including holes exposing at least a portion of the passivation layer;
• a second interlayer insulating layer formed on the first interlayer insulating layer such that air is trapped in the holes;
• a plurality of reroutings formed on the second interlayer insulating layer, wherein a portion of each of the reroutings is respectively in contact with each of the bonding pads;
• a third interlayer insulating layer formed on the wafer including the reroutings, the third interlayer insulating layer formed to expose a portion of each of the reroutings;
• and
• a plurality of external connecting terminals respectively bonded to each of the exposed portions of the reroutings.

A method for manufacturing a wafer level chip scale package, the method comprising:

• forming a passivation layer on a wafer including a pad so that the pad is exposed;
• forming an insulating member on the passivation layer, the insulating layer including a plurality of spaces to trap air;
• forming a rerouting on the insulating member, where a portion of the rerouting is formed to be in contact with the pad;
• forming an insulating layer on the wafer including the rerouting, the insulating layer exposing a portion of the rerouting;
• and
• forming an external connecting terminal to be in contact with the exposed rerouting.