Multi-chip semiconductor package

A semiconductor package comprising:

• a first thermally conductive substrate including a plurality of conductive tracks disposed on a first major surface thereof, and a metallic body covering a second opposing major surface thereof;
• a second thermally conductive substrate including a plurality of conductive tracks disposed on a first major surface thereof,
• first and second power semiconductor devices each including a first power contact on a first major surface thereof, a second power contact and a control contact on a second opposing major surface thereof;
• a first layer of conductive adhesive interposed between, and mechanically connected to, a first power contact of each power semiconductor device and a respective conductive track on said first thermally conductive substrate, a second layer of conductive adhesive interposed between, and mechanically connected to a second power contact of each power semiconductor device and a respective conductive track on said second thermally conductive substrate;
• and
• a third layer of conductive adhesive interposed between, and mechanically connected to, a control contact of each power semiconductor device and a respective conductive track, wherein said first power electrode and said first power semiconductor device and said second power electrode of said second power semiconductor device are electrically connected to one another through at least one of said conductive tracks.