Semiconductor wafer scale package system

A semiconductor wafer scale package system comprising:

• providing a semiconductor substrate having a through-hole via lined with a conductive coating including forming the through-hole via near the edge of a semiconductor device;
• forming a filled via by filling the through-hole via with a conductive material including spraying or printing the conductive material;
• coupling a package substrate to the filled via including coupling all of the filled via on the semiconductor substrate to a package substrate;
• and
• singulating a chip scale package from the semiconductor substrate and the package substrate including singulating the chip scale package.

A semiconductor wafer scale package system comprising:

• a semiconductor substrate having a through-hole via lined with a conductive coating;
• a conductive material filling the through-hole via on the conductive coating;
• and
• a package substrate having a component interconnect, the component interconnect connected to the conductive material, and the package substrate having sides characteristic of being simultaneously singulated along with the semiconductor substrate being singulated from a semiconductor wafer.