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US 2007/0164407 A1Published application
Double encapsulated semiconductor package and manufacturing method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsByung-Seok Jun, Gil-Beag Kim, Yong-Jin Lee
Life of this patent
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Abstract
A double encapsulated semiconductor package and manufacturing methods of forming the same are provided. Embodiments of the semiconductor package include a complex chip having normal and random pads formed on its active surface, the complex chip being attached to a first surface of a wiring substrate. First and second windows are formed in the wiring substrate to respectively expose the normal and random pads, and to allow bonding wires to be connected to the normal and random pads with the wiring substrate. A first resin encapsulation portion is formed by a molding method in the first window and a second resin encapsulation portion is formed by a potting method in the second window.
Claims24
A semiconductor package comprising:
- a complex chip having an active surface, the complex chip including a plurality of normal pads and random pads formed on the active surface of the complex chip;
- a wiring substrate having a first surface and a second surface, wherein the active surface of the complex chip is attached to the first surface, and first windows and second windows are formed such that the normal pads and random pads are respectively exposed through the first windows and the second windows;
- a plurality of bonding wires electrically connecting the normal pads and the random pads to the wiring substrate through the first and second windows, respectively;
- a first resin encapsulation portion formed by a molding method to cover the complex chip installed on the first surface and cover the first windows;
- and
- a second resin encapsulation portion formed by a potting method to cover the second windows.
3 more elements
A manufacturing method of a semiconductor chip package comprising:
- (a) providing a complex chip having an active surface, the complex chip including normal pads and random pads formed on the active surface of the complex chip;
- (b) attaching the active surface of the complex chip on a first surface of a wiring substrate such that the normal pads are exposed through first windows of the wiring substrate and the random pads are exposed through second windows of the wiring substrate;
- (c) electrically connecting the normal and random pads to the wiring substrate with bonding wires through the first and second windows, respectively;
- (d) forming a first resin encapsulation portion by substantially simultaneously encapsulating the semiconductor chip installed on the first surface of the wiring substrate and substantially filling the first windows formed through the wiring substrate in a molding method;
- (e) forming a second resin encapsulation portion by substantially filling the second windows formed through the wiring substrate in a potting method;
- and
- (f) forming solder balls on the second surface.
4 more elements
A semiconductor chip package comprising:
- semiconductor chips including a normal chip formed with normal pads on its active surface and a complex chip formed with normal pads and random pads on its active surface;
- a wiring substrate having a first surface and a second surface, wherein the active surface of at least one of the semiconductor chips is attached to the first surface such that first windows formed through the wiring substrate correspond to the normal pads of the attached semiconductor chip, and second windows formed through the wiring substrate correspond to the random pads of the complex chip;
- a plurality of bonding wires electrically connecting the normal and random pads to the wiring substrate through the first windows and the second windows, respectively;
- a first resin encapsulation portion formed by a molding method to cover the semiconductor chips installed on the first surface and the first windows;
- a second resin encapsulation portion formed by a potting method to cover the second windows;
- and
- a plurality of solder balls formed on the second surface of the wiring substrate.
4 more elements
A manufacturing method of a semiconductor chip package comprising:
- (a) providing semiconductor chips including a normal chip formed with normal pads on its active surface and a complex chip formed with normal pads and random pads on its active surface;
- (b) attaching the active surface of at least one of the semiconductor chips on a first surface of a wiring substrate such that the normal pads are exposed through first windows of the wiring substrate and the random pads are exposed through second windows of the wiring substrate;
- (c) electrically connecting the normal and random pads to the wiring substrate with bonding wires through the first and second windows, respectively;
- (d) forming a first resin encapsulation portion to substantially simultaneously cover the semiconductor chips installed on the first surface and the first windows by a molding method;
- (e) forming a second resin encapsulation portion to cover the second windows by a potting method;
- and
- (f) forming solder balls on the second surface.
4 more elements
A method of manufacturing a semiconductor chip package comprising:
- attaching a complex semiconductor chip having an active surface and including normal pads and random pads formed on the active surface to a first surface of a wiring substrate including first and second windows, where the normal pads and random pads are respectively exposed through the first and second windows of the wiring substrate;
- electrically connecting the normal pads and random pads of the complex semiconductor chip to a second surface of the wiring substrate through the first and second windows, respectively;
- performing a molding encapsulation process to form a first resin encapsulation portion over the complex semiconductor chip and substantially filling the first windows;
- performing a potting encapsulation process to form a second resin encapsulation portion substantially filling the second windows;
- and
- forming solder balls on the second surface of the wiring substrate.
3 more elements
Dependencies are inferred from the claim text.