Semiconductor package and process for making the same
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorsDae-Hoon Jung, Seok-Won Lee, Sang-Bae Park
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Abstract
A semiconductor package mainly includes a leadframe and a first semiconductor chip such as an application specific integrated circuit (ASIC) encapsulated in a first package body having a cavity for receiving a second semiconductor chip such as a pressure sensor chip, and a cover disposed over the cavity of the first package body. At least a portion of the first package body is formed between the second semiconductor chip and the die pad such that the second semiconductor chip is directly disposed on the portion of the first package body instead of the die pad.
Claims14
A semiconductor package comprising:
- a leadframe having a die pad and a plurality of first and second leads arranged about the periphery of the die pad;
- a first semiconductor chip securely attached to a lower surface of the die pad, the first semiconductor chip being electrically coupled to the first and second leads;
- a first package body encapsulating the first semiconductor chip, the die pad and at least a portion of each of the first and second leads, the first package body having a cavity exposing an upper surface of an inner lead portion of each of the second leads;
- a second semiconductor chip disposed in the cavity of the first package body and above an upper surface of the die pad, the second semiconductor chip being electrically coupled to the inner lead portions of the second leads;
- and
- a cover disposed over the cavity of the first package body,
- wherein at least a portion of the first package body is formed between the second semiconductor chip and the die pad.
A process for making a semiconductor package, comprising:
- providing a leadframe having a die pad and a plurality of first and second leads arranged about the periphery of the die pad;
- attaching a first semiconductor chip onto the die pad of the leadframe;
- electrically coupling the first semiconductor chip to the first and second leads of the leadframe;
- encapsulating the first semiconductor chip, the die pad and at least a portion of each of the first and second leads in a first package body having a cavity exposing an inner lead portion of each of the second leads, wherein at least a portion of the first package body is formed on an upper surface of the die pad;
- mounting a second semiconductor chip in the cavity of the first package body and upon the portion of the first package body on the upper surface of the die pad;
- electrically coupling the second semiconductor chip to the inner lead portions of the second leads;
- and
- disposing a cover over the cavity of the first package body.
Dependencies are inferred from the claim text.