Chip package with built-in capacitor structure

A chip package with built-in capacitor structure, comprising:

• an integrated circuit (IC) unit, having an active surface;
• a capacitor unit, disposed on the active surface, the capacitor unit comprising:
• a first metal foil, disposed on the active surface;
• a second metal foil;
• and
• a dielectric layer, disposed between the first metal foil and the second metal foil;
• a carrier, disposed on a surface away from the dielectric layer of the second metal foil, wherein the first metal foil is electrically connected to the carrier, the second metal foil is electrically connected to the carrier, the IC unit is electrically connected to the carrier, the IC unit is electrically connected to the first metal foil, and the IC unit is electrically connected to the second metal foil;
• and
• a molding compound, disposed on the carrier for fixing the IC unit, the capacitor unit, and the carrier.

A chip package with built-in capacitor structure, comprising:

• an IC unit, having an active surface;
• a capacitor unit, disposed on the active surface, the capacitor unit comprising:
• a first metal foil, disposed on the active surface, the first metal foil having a first opening exposing a part of the IC unit;
• a dielectric layer, disposed on a surface of the first metal foil, the dielectric layer having a second opening connected to the first opening;
• a second metal foil, disposed on a surface away from the first metal foil of the dielectric layer, the second metal foil having a third opening, wherein the third opening is connected to the second opening and exposes a part of the first metal foil together with the second opening;
• a carrier, having a plurality of pins, the carrier being disposed on the surface away from the dielectric layer of the second metal foil;
• a plurality of leads, electrically connected between the first metal foil and the pins, between the second metal foil and the pins, between the IC unit and the pins, between the IC unit and the first metal foil, and between the IC unit and the second metal foil;
• and
• a molding compound, disposed on the carrier for fixing the IC unit, the capacitor unit, and the carrier.

A chip package with built-in capacitor structure, comprising:

• an IC unit, having an active surface;
• a capacitor unit, disposed on the active surface, the capacitor unit comprising:
• a first metal foil, disposed on the active surface, the first metal foil having a first opening exposing a part of the capacitor unit;
• a dielectric layer, disposed on a surface of the first metal foil, the dielectric layer having a second opening connected to the first opening;
• a second metal foil, disposed on another surface away from the first metal foil of the dielectric layer, the second metal foil having a third opening, wherein the third opening is connected to the second opening and exposes a part of the first metal foil together with the second opening;
• a carrier, disposed on the surface away from the dielectric layer of the second metal foil, the carrier comprising:
• a substrate, disposed on the surface away from the dielectric layer of the second metal foil;
• a patterned circuit layer, disposed on the surface away from the second metal foil of the substrate;
• a plurality of leads, electrically connected between the first metal foil and the patterned circuit layer, between the second metal foil and the patterned circuit layer, between the IC unit and the patterned circuit layer, between the IC unit and the first metal foil, and between the IC unit and the second metal foil;
• and
• a molding compound, disposed on the carrier for fixing the IC unit, the capacitor unit, and the carrier.