Structure and method for MOSFET gate electrode landing pad
AssigneeInternational Business Machines Corporation
InventorsLawrence Clevenger, Timothy Dalton, Louis Hsu, Carl Radens, Keith Wong, Chih-Chao Yang
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Abstract
A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.
Claims35
An integrated circuit comprising:
- a substrate;
- a first gate electrode over said substrate;
- a second gate electrode over said substrate;
- and
- a landing pad comprising a pair of flanged ends overlapping said second gate electrode,
- wherein the structure of said second gate electrode is discontinuous with the structure of said landing pad.
A microelectronic device comprising:
- a substrate;
- a first gate electrode over said substrate;
- a second gate electrode over said substrate;
- and
- a landing pad comprising a pair of flanged ends overlapping said second gate electrode,
- wherein the structure of said second gate electrode is discontinuous with the structure of said landing pad,
- wherein a width of said landing pad is greater than a width of said second gate electrode, and
- wherein an upper surface of said landing pad is higher than an upper surface of said first gate electrode.
A field effect transistor (FET) comprising:
- a substrate;
- a buried oxide (BOX) layer over said substrate;
- a silicon on insulator (SOI) layer over said BOX layer;
- a shallow trench isolation (STI) region over said BOX layer;
- a first gate structure on said SOI layer;
- a second gate structure on said STI region;
- and
- a landing pad attached to said second gate structure, wherein a width of said landing pad is greater than a width of said second gate structure, and
- wherein the structure of said second gate structure is discontinuous with the structure of said landing pad.
A method of forming an integrated circuit, said method comprising:
- providing a substrate;
- patterning a first gate electrode over said substrate, patterning a second gate electrode over said substrate;
- and
- forming a landing pad comprising a pair of flanged ends and overlapping said second gate electrode,
- wherein the structure of said second gate electrode is discontinuous with the structure of said landing pad.
A method of forming a field effect transistor (FET), said method comprising:
- providing a substrate;
- depositing a buried oxide (BOX) layer over said substrate;
- positioning a silicon on insulator (SOI) layer over said BOX layer;
- forming a shallow trench isolation (STI) region over said BOX layer;
- patterning a first gate structure on said SOI layer;
- patterning a second gate structure on said STI region;
- and
- attaching a landing pad to said second gate structure,
- wherein a width of said landing pad is greater than a width of said second gate structure, and
- wherein the structure of said second gate structure is discontinuous with the structure of said landing pad.
Dependencies are inferred from the claim text.