Semiconductor device of high breakdown voltage and manufacturing method thereof
OwnerTae-Pok Rheeinventor
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Abstract
Disclosed are a semiconductor device of high breakdown voltage and a method manufacturing the same. According to the invention, it is possible to previously prevent an increase size of the device due to a separation of a high concentration impurity layer and a gate electrode pattern by embedding the gate electrode pattern in a bottom of a semiconductor substrate, and sequentially stacking a low concentration impurity layer and a high concentration impurity layer for source/drain diffusion layers on both sides of the gate electrode pattern, thereby allowing the high concentration impurity layer to easily secure a voltage drop areas necessary for itself without being spaced from the gate electrode pattern.
Claims12
A semiconductor device of high breakdown voltage comprising:
- a gate electrode pattern embedded in an active area of a semiconductor substrate, which area is defined by a device separating film having an inversion preventing layer;
- a gate insulating layer pattern surrounding the gate electrode pattern;
- high concentration impurity layers located on both sides of the gate electrode pattern to contact the gate insulating layer pattern and formed in an upper layer of the active area of the semiconductor substrate by an ion implantation;
- and
- low concentration impurity layers located on both sides of the gate electrode pattern to contact the gate insulating layer pattern and formed under the high concentration impurity layers by an ion implantation.
A method of manufacturing a semiconductor device of high breakdown voltage comprising steps of:
- forming a trench in an active area of a semiconductor substrate;
- forming a gate insulating layer pattern on a surface of the trench;
- forming a gate electrode pattern in the trench to contact the gate insulating layer pattern;
- forming low concentration impurity layers in the active area of the semiconductor substrate to contact the gate insulating layer pattern and to be located on both sides of the gate electrode pattern by an ion implantation;
- and
- forming high concentration impurity layers on the low concentration impurity layers to contact the gate insulating layer pattern and to be located on both sides of the gate electrode pattern by an ion implantation.
Dependencies are inferred from the claim text.