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US 2007/0164352 A1Published application
Multi-bit-per-cell nvm structures and architecture
AssigneeThe Regents of the University of California
InventorsAlvaro Padilla, Tsu-Jae King
Life of this patent
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Abstract
A transistor structure, such as a Double-gated FET (DG FET), that has been modified to include a charge-trapping region used to store either 2- or 4-bits of information. The charge-trapping region can, for example, be embedded in the gate dielectric stack underneath each gate electrode, or placed on the sidewalls of each gate electrode.
Claims39
An apparatus, comprising:
- a transistor structure;
- said transistor structure having at least one gate electrode;
- said transistor structure having at least one charge-trapping region configured to store a bit of information;
- wherein off-state current is utilized to distinguish charge state of said bit in said transistor structure.
1 more element
An apparatus, comprising:
- a transistor structure;
- said transistor structure having at least one gate electrode;
- said transistor structure having at least one charge-trapping region;
- wherein the at least one gate electrode and the at least one charge-trapping region are configured for storing 2 bits of information;
- wherein off-state current is utilized to distinguish charge state of said bit in said transistor structure.
2 more elements
An apparatus, comprising:
- a transistor structure;
- said transistor structure having at least one gate electrode;
- said transistor structure having at least one charge-trapping region;
- wherein said at least one gate electrode and said at least one charge-trapping region are configured for storing 4 bits of information;
- and
- wherein off-state current is utilized to distinguish charge state of said bit in said transistor structure.
3 more elements
An apparatus, comprising:
- a transistor structure;
- said transistor structure having at least one charge-trapping region;
- wherein said transistor structure has a plurality of gate electrodes;
- wherein said at least one charge-trapping region and said plurality of gate electrodes are configured for storing 4 bits of information;
- and
- wherein off-state current is utilized to distinguish charge state of said bit in said transistor structure.
3 more elements
Dependencies are inferred from the claim text.