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US 2007/0164350 A1Published application
Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device
AssigneeMicron Technology, Inc.
InventorsFrederick Fishburn, Terrence McDaniel, Richard Lane
Life of this patent
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Abstract
A method used to form a semiconductor device provides a silicide layer on a plurality of transistor word lines and on a plurality of conductive plugs. In one embodiment, the word lines, one or more sacrificial dielectric layers on the word lines, conductive plugs, and a conductive enhancement layer are formed through the use of a single mask. An in-process semiconductor device which may be formed using one embodiment of the inventive method is also described.
Claims11
An in-process semiconductor device comprising:
- a word line comprising first and second vertically oriented surfaces and a horizontally oriented surface;
- first and second spacers, each spacer comprising a vertically oriented surface having a first portion which contacts the word line and a second portion which is exposed;
- and
- first and second conductive plugs, each comprising:
- a first exposed surface which forms a generally continuous vertically oriented surface with the second portion of one of the spacers;
- and
- a second surface which contacts the one spacer with which it forms the generally continuous vertically oriented surface.
4 more elements
A semiconductor device comprising:
- first and second conductive plugs each having a horizontally oriented surface and a vertically oriented surface;
- a conductive transistor control gate interposed between the first and second conductive plugs, the conductive transistor control gate having first and second vertically oriented surfaces and a horizontally oriented surface;
- first and second dielectric spacers each having a top surface and first and second vertically oriented surfaces, wherein the first vertically oriented surface of the first and second dielectric spacers each contact one of the first and second vertically oriented surfaces of the conductive transistor control gate, and the second vertically oriented surface of the first and second dielectric spacers each contact the vertically oriented surface of one of the first and second conductive plugs, and the top surface of each spacer is above the horizontally oriented surface of the conductive transistor control gate;
- and
- a conductive layer comprising:
- a first portion which electrically contacts the horizontally oriented surface of the conductive transistor control gate;
- a second portion which contacts the first vertically oriented surface of the first and second dielectric spacers;
- and
- a third portion which electrically contacts the horizontally oriented surface of each conductive plug.
6 more elements
An in-process semiconductor device, comprising:
- a conductive transistor gate having first and second vertically oriented sidewalls;
- a dielectric layer overlying the conductive transistor gate, wherein the dielectric layer comprises a horizontally oriented lower surface, a horizontally oriented upper surface, and first and second vertically oriented sidewalls;
- and
- first and second spacers each comprising a vertically oriented sidewall and an upper extent, wherein:
- the first vertically oriented sidewall of the first spacer contacts the first vertically oriented sidewall of the transistor gate and the first vertically oriented sidewall of the dielectric layer;
- and
- the second vertically oriented sidewall of the second spacer contacts the second vertically oriented sidewall of the transistor gate and the second vertically oriented sidewall of the dielectric layer,
- wherein the upper extent of each spacer is at a level above the lower surface of the dielectric layer and below the upper surface of the dielectric layer.
5 more elements
Dependencies are inferred from the claim text.