Semiconductor device

A semiconductor device, comprising:

• a divider resistor circuit that is configured to obtain a voltage output through voltage division and adjust the voltage output through cutting one or more fuse elements;
• the divider resistor circuit including
• a plurality of resistance value adjusting resistor elements he that are serially connected;
• a plurality of fuse MOS transistors as the fuse elements that are connected in parallel to the resistance value adjusting resistor elements;
• a nonvolatile memory cell that includes a memory transistor and a selection transistor, the memory transistor being realized by a MOS transistor including a memory gate oxide film that is arranged on a semiconductor substrate and a floating gate made of polysilicon that is arranged on the memory gate oxide film which floating gate is in an electrically floating state, and the selection transistor being realized by a MOS transistor serially connected to the memory transistor and including a selection gate oxide film that is arranged on the semiconductor substrate and a selection gate made of polysilicon that is arranged on the selection gate oxide film;
• and
• a read circuit for switching on/off the fuse MOS transistors according to the storage state of the nonvolatile memory cell;
• wherein at least one of the fuse MOS transistors and the read circuit is configured as a peripheral circuit transistor realized by a MOS transistor including a peripheral circuit gate oxide film that is arranged on the semiconductor substrate, and a peripheral circuit gate made of polysilicon that is arranged on the peripheral circuit gate oxide film which peripheral circuit gate oxide film is arranged to be thicker than the memory gate oxide film.

A semiconductor device comprising:

• a voltage detecting circuit that includes a divider resistor circuit that divides an input voltage and outputs the divided voltage, a reference voltage generating circuit that generates a reference voltage, and a comparator circuit that compares the divided voltage from the divider resistor circuit with the reference voltage from the reference voltage generating circuit;
• the divider resistor circuit including
• a plurality of resistance value adjusting resistor elements the that are serially connected;
• a plurality of fuse MOS transistors as the fuse elements that are connected in parallel to the resistance value adjusting resistor elements;
• a nonvolatile memory cell that includes a memory transistor and a selection transistor, the memory transistor being realized by a MOS transistor including a memory gate oxide film that is arranged on a semiconductor substrate and a floating gate made of polysilicon that is arranged on the memory gate oxide film which floating gate is in an electrically floating state, and the selection transistor being realized by a MOS transistor serially connected to the memory transistor and including a selection gate oxide film that is arranged on the semiconductor substrate and a selection gate made of polysilicon that is arranged on the selection gate oxide film;
• and
• a read circuit for switching on/off the fuse MOS transistors according to the storage state of the nonvolatile memory cell;
• wherein at least one of the fuse MOS transistors and the read circuit is configured as a peripheral circuit transistor realized by a MOS transistor including a peripheral circuit gate oxide film that is arranged on the semiconductor substrate, and a peripheral circuit gate made of polysilicon that is arranged on the peripheral circuit gate oxide film which peripheral circuit gate oxide film is arranged to be thicker than the memory gate oxide film.

A semiconductor device comprising:

• a constant voltage generating circuit that includes an output driver that controls output of an input voltage, a divider resistor circuit that divides an output voltage and outputs the divided voltage, a reference voltage generating circuit that generates a reference voltage, and a comparator circuit that compares the divided voltage from the divider resistor circuit with the reference voltage from the reference voltage generating circuit and controls an operation of the output driver according to the comparison result;
• the divider resistor circuit including
• a plurality of resistance value adjusting resistor elements that are serially connected;
• a plurality of fuse MOS transistors as the fuse elements that are connected in parallel to the resistance value adjusting resistor elements;
• a nonvolatile memory cell that includes a memory transistor and a selection transistor, the memory transistor being realized by a MOS transistor including a memory gate oxide film that is arranged on a semiconductor substrate and a floating gate made of polysilicon that is arranged on the memory gate oxide film which floating gate is in an electrically floating state, and the selection transistor being realized by a MOS transistor serially connected to the memory transistor and including a selection gate oxide film that is arranged on the semiconductor substrate and a selection gate made of polysilicon that is arranged on the selection gate oxide film;
• and
• a read circuit for switching on/off the fuse MOS transistors according to the storage state of the nonvolatile memory cell;
• wherein at least one of the fuse MOS transistors and the read circuit is configured as a peripheral circuit transistor realized by a MOS transistor including a peripheral circuit gate oxide film that is arranged on the semiconductor substrate, and a peripheral circuit gate made of polysilicon that is arranged on the peripheral circuit gate oxide film which peripheral circuit gate oxide film is arranged to be thicker than the memory gate oxide film.

A semiconductor device comprising:

• a semiconductor substrate;
• a nonvolatile memory cell that includes
• a memory transistor realized by a MOS transistor including a memory gate oxide film that is arranged on the semiconductor substrate, and a floating gate made of polysilicon that is arranged on the memory gate oxide film which floating gate is in an electrically floating state;
• and
• a selection transistor realized by a MOS transistor that is serially connected to the memory transistor, the selection transistor including a selection gate oxide film that is arranged on the semiconductor substrate, and a selection gate made of polysilicon that is arranged on the selection gate oxide film;
• and
• a peripheral circuit transistor realized by a MOS transistor including a peripheral circuit gate oxide film that is arranged on the semiconductor substrate, and a peripheral circuit gate made of polysilicon that is arranged on the peripheral circuit gate oxide film;
• wherein an impurity concentration within the polysilicon of the floating gate is arranged to be lower than an impurity concentration within the polysilicon of the peripheral circuit gate oxide film.

A semiconductor device, comprising:

• a divider resistor circuit that is configured to obtain a voltage output through voltage division and adjust the voltage output through cutting one or more fuse elements;
• the divider resistor circuit including
• a plurality of resistance value adjusting resistor elements that are serially connected;
• a plurality of fuse MOS transistors as the fuse elements that are connected in parallel to the resistance value adjusting resistor elements;
• a nonvolatile memory cell that includes a memory transistor and a selection transistor, the memory transistor being realized by a MOS transistor including a memory gate oxide film that is arranged on a semiconductor substrate and a floating gate made of polysilicon that is arranged on the memory gate oxide film which floating gate is in an electrically floating state, and the selection transistor being realized by a MOS transistor serially connected to the memory transistor and including a selection gate oxide film that is arranged on the semiconductor substrate and a selection gate made of polysilicon that is arranged on the selection gate oxide film;
• and
• a read circuit for switching on/off the fuse MOS transistors according to the storage state of the nonvolatile memory cell;
• wherein at least one of the fuse MOS transistors and the read circuit is configured as a peripheral circuit transistor realized by a MOS transistor including a peripheral circuit gate oxide film that is arranged on the semiconductor substrate, and a peripheral circuit gate made of polysilicon that is arranged on the peripheral circuit gate oxide film, the polysilicon of the peripheral circuit gate being arranged to have an impurity concentration that is higher than an impurity concentration within the polysilicon of the floating gate.

A semiconductor device comprising:

• a voltage detecting circuit that includes a divider resistor circuit that divides an input voltage and outputs the divided voltage, a reference voltage generating circuit that generates a reference voltage, and a comparator circuit that compares the divided voltage from the divider resistor circuit with the reference voltage from the reference voltage generating circuit;
• the divider resistor circuit including
• a plurality of resistance value adjusting resistor elements that are serially connected;
• a plurality of fuse MOS transistors as the fuse elements that are connected in parallel to the resistance value adjusting resistor elements;
• a nonvolatile memory cell that includes a memory transistor and a selection transistor, the memory transistor being realized by a MOS transistor including a memory gate oxide film that is arranged on a semiconductor substrate and a floating gate made of polysilicon that is arranged on the memory gate oxide film which floating gate is in an electrically floating state, and the selection transistor being realized by a MOS transistor serially connected to the memory transistor and including a selection gate oxide film that is arranged on the semiconductor substrate and a selection gate made of polysilicon that is arranged on the selection gate oxide film;
• and
• a read circuit for switching on/off the fuse MOS transistors according to the storage state of the nonvolatile memory cell;
• wherein at least one of the fuse MOS transistors and the read circuit is configured as a peripheral circuit transistor realized by a MOS transistor including a peripheral circuit gate oxide film that is arranged on the semiconductor substrate, and a peripheral circuit gate made of polysilicon that is arranged on the peripheral circuit gate oxide film, the polysilicon of the peripheral circuit gate being arranged to have an impurity concentration that is higher than an impurity concentration within the polysilicon of the floating gate.

A semiconductor device comprising:

• a constant voltage generating circuit that includes an output driver that controls output of an input voltage, a divider resistor circuit that divides an output voltage and outputs the divided voltage, a reference voltage generating circuit that generates a reference voltage, and a comparator circuit that compares the divided voltage from the divider resistor circuit with the reference voltage from the reference voltage generating circuit and controls an operation of the output driver according to the comparison result;
• the divider resistor circuit including
• a plurality of resistance value adjusting resistor elements that are serially connected;
• a plurality of fuse MOS transistors as the fuse elements that are connected in parallel to the resistance value adjusting resistor elements;
• a nonvolatile memory cell that includes a memory transistor and a selection transistor, the memory transistor being realized by a MOS transistor including a memory gate oxide film that is arranged on a semiconductor substrate and a floating gate made of polysilicon that is arranged on the memory gate oxide film which floating gate is in an electrically floating state, and the selection transistor being realized by a MOS transistor serially connected to the memory transistor and including a selection gate oxide film that is arranged on the semiconductor substrate and a selection gate made of polysilicon that is arranged on the selection gate oxide film;
• and
• a read circuit for switching on/off the fuse MOS transistors according to the storage state of the nonvolatile memory cell;
• wherein at least one of the fuse MOS transistors and the read circuit is configured as a peripheral circuit transistor realized by a MOS transistor including a peripheral circuit gate oxide film that is arranged on the semiconductor substrate, and a peripheral circuit gate made of polysilicon that is arranged on the peripheral circuit gate oxide film, the polysilicon of the peripheral circuit gate being arranged to have an impurity concentration that is higher than an impurity concentration within the polysilicon of the floating gate.