Nonvolatile Semiconductor Memory Device Comprising Shield Electrode On Source and Method For Manufacturing the Same

A nonvolatile semiconductor memory device comprising:

• memory cells each including a charge accumulation layer and a control gate formed on the charge accumulation with an inter-gate insulating film interposed therebetween;
• a memory cell array including the memory cells arranged in a matrix on a semiconductor substrate, the memory cells adjacent to each other in a column direction of the memory cell array sharing a source or a drain;
• word lines each connecting commonly the control gates of the memory cells in a same row of the memory cell array;
• bit lines each connecting commonly drains of the memory cells in the same column of the memory cell array;
• diffusion layers each formed in a surface of the semiconductor substrate located between the sources adjacent to each other in a row direction of the memory cell array to electrically connect the sources adjacent to each other in the row direction together, a surface of an area of the semiconductor substrate in which the diffusion layer is formed being lower than a surface of an area of the semiconductor substrate in which the sources are formed;
• and
• shield wires each formed on the source and the diffusion layer, a top surface of the shield wire being lower than that of the charge accumulation layer.

A method for fabricating a nonvolatile semiconductor memory device comprising:

• forming floating gates of a memory cell on a semiconductor substrate in a matrix;
• forming word lines on the floating gates arranged in the same row direction;
• making trenches in the semiconductor substrate so that each trench is located between areas in which source areas of the memory cell which are adjacent to each other in the row direction are to be formed;
• forming the source areas in a surface of the semiconductor substrate so that each of the source areas is shared by the floating gates adjacent to each other in a column direction;
• forming drain areas in the surface of the semiconductor substrate so that each of the drain areas is adjacent to the source area with the floating gate interposed therebetween in the column direction and is wider than the source area in the column direction;
• forming diffusion layers on inner wall portions of the trenches along the row direction so as to connect the source areas adjacent to each other in the same row direction, so that the source area and the diffusion layer form a source line;
• forming a shield wire on each of the source lines, a top surface of the shield wire being lower than that of the floating gate adjacent to the shield wire;
• and
• forming bit lines in the column direction, each of the bit lines being electrically connected to the drain area via a drain contact.