Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsMasaru Kidoh, Hideaki Aochi, Ryota Katsumata, Masaru Kito
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Abstract
A semiconductor memory device excellent in data holding characteristics even when a cell area is reduced is disclosed. According to one aspect of the present invention, a semiconductor memory device comprises a transistor including a source, a drain and a channel region disposed in a semiconductor substrate, and including a gate electrode disposed through a gate insulator on a surface of the semiconductor substrate of the channel region, a capacitor connected to the channel region, a first wiring line electrically connected to the gate electrode, and a second wiring line electrically connected to the drain.
Claims19
A semiconductor memory device comprising:
- a transistor including a source, a drain and a channel region disposed in a semiconductor substrate, and a gate electrode disposed through a gate insulator on a surface of the semiconductor substrate of the channel region;
- a capacitor connected to the channel region;
- a first wiring line electrically connected to the gate electrode;
- and
- a second wiring line electrically connected to the drain.
A semiconductor memory device comprising:
- a plurality of trenches disposed in a semiconductor substrate;
- a transistor including a drain, a channel region, and a source disposed in a columnar semiconductor substrate area held between the trenches, and a gate electrode disposed through a gate insulator on one side face of the channel region and disposed in a trench;
- a capacitor connected to the other side face of the channel region and disposed in another trench;
- a first wiring line electrically connected to the gate electrode;
- and
- a second wiring line electrically connected to the drain.
Dependencies are inferred from the claim text.