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AssigneeInternational Business Machines Corporation
InventorsJames Adkisson, Charles Black, Alfred Grill, Randy Mann, Deborah Neumayer, Wilbur Pricer, Katherine Saenger, Thomas Shaw
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A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.
A FE delivery wafer comprising a carrier substrate, a sacrificial release layer located on a surface of said carrier substrate, a first conductive layer located on a surface of said sacrificial release layer, a ferroelectric layer located on a surface of said first conductive layer, and a second conductive layer that is located on a surface of said ferroelectric layer and is also located on an outermost surface of said FE delivery wafer.
A FE delivery wafer comprising a carrier substrate, a sacrificial release layer located on a surface of said carrier substrate, at least one level within each of which a patterned dielectric layer and a patterned conductive layer are located complementarily to fill each of said level, a ferroelectric layer located on a surface of said conductive layer, and an outermost conductive layer, wherein said outermost conductive layer is located on an outermost surface of said FE delivery wafer.
Dependencies are inferred from the claim text.