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US 2007/0164319 A1Published application
Silicon pillars for vertical transistors
AssigneeMicron Technology, Inc.
InventorPatrick Thomas
Life of this patent
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Abstract
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon.
Claims22
A masking structure for forming semiconductor devices, the masking structure comprising:
- a substrate;
- a first hard mask over the substrate, wherein the first hard mask comprises a plurality of parallel lines;
- and
- a second hard mask directly over a portion of the first hard mask, wherein the second hard mask is a plurality of islands on the lines of the first hard mask.
1 more element
A memory array comprising:
- a semiconductor substrate;
- a first set of trenches etched a first amount to a first depth in the semiconductor substrate;
- a second set of trenches etched the first amount and a second amount to a second depth in the semiconductor substrate, wherein the second set of trenches is substantially orthogonal to the first set of trenches, and wherein the first depth is approximately equal to the difference between the second depth and the second amount;
- wherein the first and second sets of trenches define an array of vertically extending pillars, wherein each pillar in the array of vertically extending pillars comprises a drain region and a body region to form a vertical transistor;
- a plurality of wordlines formed within at least a portion of the first set of trenches and between adjacent vertical transistors;
- a plurality of body lines formed within at least a portion of the first set of trenches and between vertical transistors, wherein the wordlines and body lines are alternatingly disposed within the array;
- and
- a plurality of bit lines formed with at least a portion of the second set of trenches.
5 more elements
An integrated circuit comprising:
- a semiconductor substrate;
- a first set of trenches etched into the semiconductor substrate a first amount to a first depth;
- and
- a second set of trenches etched into the semiconductor substrate the first amount and a second amount to a second depth, wherein the second set of trenches crosses the first set of trenches, wherein the first depth is approximately equal to the difference of the second depth and the second amount, and wherein a silicon structure protruding among the first and second sets of trenches is formed in the substrate.
1 more element
Dependencies are inferred from the claim text.