Multi-standard multi-rate filter
AssigneeCSR Technology Inc.
InventorsMark Sturza, Donald Leimer
Life of this patent
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Abstract
A method is provided for decimating a digital signal by a factor of M and matching it to a desired channel bandwidth. The method applies the digital signal input samples to a (M−1) stage tapped delay line, downsamples the input samples and the output samples of each tapped delay line stage by a factor of M, and applies each of the M downsampled sample value streams to M allpass IRR filters, respectively. The M allpass IRR filtered sample streams are then summed and scaled by a factor of 1/M. The result can then be filtered by a digital channel filter.
Claims24
A method for decimating a digital signal by a factor of M and matching it to a desired channel bandwidth, comprising:
- a. Applying said digital signal input samples to a M−1 stage tapped delay line;
- b. Downsampling said input samples and outputs of said tapped delay line stages by a factor of M;
- c. Applying said M downsampled values to M allpass IRR filters where the phase of said allpass IRR filters add constructively at frequencies below a passband frequency, and add destructively at frequencies above a stopband frequency, and where:
- i. Said passband frequency is less than the input sample rate divided by 2 times M
- ii. Said stopband frequency is greater than the input sample rate divided by 2 times M;
- d. Summing the outputs of said M allpass filters;
- e. Scaling said sum by a factor of 1/M;
- f. Applying said scaled sum to a digital channel filter.
A method for selectively decimating a digital signal by a factor equal to the product of any number of the positive integers M1, M2, . . . , and Mn, and matching it to a desired channel bandwidth comprising the steps of:
- a. Setting a buffer equal to said digital signal to be decimated;
- b. Setting k equal to 1;
- c. If said Mk is in said product, inputting said buffer to the input of a Mk-path decimate by Mk method and placing output in said buffer;
- d. Incrementing said k;
- e. If k less than or equal to n, going to step c;
- f. Applying said buffer to a digital channel filter.
A quad rate, multi-standard decimation device with decimation ratio selectable from 2, 3, 4, and 6;
- and selectable mode, comprising:
- a. A first input switch with one branch for decimate by 3, 4, or 6;
- and a second branch for decimate by 2;
- b. A first digital filter connected to said first input switch decimate by 3, 4, or 6 branch;
- c. A second switch with input connected to said first digital filter output with one branch for decimate by 4 or 6, and a second branch for decimate by 3;
- d. A downsample by 2 connected to said second switch decimate by 4 or 6 branch;
- e. A first switching mechanism selecting output of said decimate by 2 or decimate by 3 branch of said second switch depending on which path has been selected;
- f. A second switching mechanism selecting output of said first switching mechanism or decimate by 2 branch of said first switch depending on which path has been selected;
- g. A third switch connected to the output of said second switching mechanism with one branch for decimate by 3 or 6, and a second branch for decimate by 2 or 4;
- h. A combined digital filter, decimate by 3 device connected to said third switch decimate by 3 or 6 output;
- i. A combined digital filter, decimate by 2 device connected to said third switch decimate by 2 or 4 output;
- j. A third switching mechanism selecting output of said combined digital filter, decimate by 3 device or output of said combined digital filter, decimate by 2 device depending on which path has been selected;
- k. A second digital filter connected to output of said third switching mechanism;
- l. Said second digital filter bandwidth dependent on selected said mode.
Dependencies are inferred from the claim text.