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US 2007/0140637 A1Published application
Method for high topography patterning
AssigneeImec
InventorsStaf Verhaegen, Axel Nackaerts
Life of this patent
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Abstract
One inventive aspect is related to a method for isolating structures of a semiconductor material, comprising providing a pattern of the semiconductor material comprising at least one elevated line, defining device regions in the pattern, the device regions each comprising at least said at least one elevated line, and modifying the conductive properties of the semiconductor material outside said device regions, such that the device regions are electrically isolated.
Claims16
A method of isolating structures of a semiconductor material, the method comprising:
- providing a pattern of the semiconductor material comprising at least one elevated-line;
- defining device regions in the pattern, the device regions each comprising the at least one elevated line;
- and
- modifying the conductive properties of the semiconductor material outside the device regions, such that the device regions are electrically isolated.
1 more element
A multi-gate device comprising:
- a pattern comprising at least one elevated line of a semiconductor material;
- and
- device regions defined in the pattern, the device regions each comprising the at least one elevated line, wherein the device regions are electrically isolated by isolation regions defined in the semiconductor material of the at least one elevated line.
Dependencies are inferred from the claim text.