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US 2007/0127594 A1Published application
Reduced complexity coding system using iterative decoding
AssigneeCellular Elements LLC
InventorsMarvin Simon, Dariush Divsalar
Life of this patent
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Abstract
A concatenated coding scheme, using an outer coder, interleaver, and the inner coder inherent in an FQPSK signal to form a coded FQPSK signal. The inner coder is modified to enable interative decoding of the outer code.
Claims15
1-8. (canceled)
A receiver, comprising:
- a modified FQPSK demodulator, an iterative decoder, which iteratively demodulates and decodes an input signal.
12-16. (canceled)
A method, comprising decoding a modified FQPSK coded signal according to an iterative decoding scheme.
An apparatus, comprising:
- at least one soft input-soft output (SISO) demodulator configured to receive information from a channel and to produce a inner decoded sequence of bits, wherein said at least one SISO demodulator is configured to use FQPSK demodulation in order to produce said inner decoded sequence of bits;
- at least one SISO outer decoder configured to receive a sequence of input bits and generate an outer decoded sequence of bits;
- wherein said apparatus is configured to use feedback from said SISO outer decoder to iteratively demodulate and decode said information received from said channel.
An apparatus, comprising:
- a first soft-input soft-output (SISO) demodulator configured to receive an first input stream and to produce a first inner decoded stream of bits;
- a second soft-input soft-output (SISO) demodulator configured to receive a second input stream and to produce a second inner decoded stream of bits;
- a first deinterleaver configured to receive said first inner decoded stream of bits and to produce a first deinterleaved stream of bits;
- a second deinterleaver configured to receive said second inner decoded stream of bits and to produce a second deinterleaved stream of bits;
- a first SISO outer decoder configured to receive said first deinterleaved stream of bits and produce an first outer decoded stream of bits;
- a second SISO outer decoder configured to receive said second deinterleaved stream of bits and produce a second outer decoded stream of bits;
- wherein said first and second SISO outer decoders are configured to provide said first and second outer decoded stream of bits as feedback to said apparatus in order for said apparatus to iteratively demodulate and decode information received at said decoder.
4 more elements
Dependencies are inferred from the claim text.