Clock and data recovery circuit

A clock and data recovery circuit comprising:

• a phase synchronization loop including an oscillator, the oscillation frequency of which is variably controlled, said phase synchronization loop performing phase-synchronization of a clock signal output from said oscillator with an input data signal;
• a discriminator circuit, responsive to a clock signal for discrimination, for discriminating said input data signal and outputting the discriminated signal;
• a phase detector circuit for detecting the phase difference between an output data signal, discriminated and output by said discriminator circuit, and said input data signal;
• and
• a phase shift circuit for shifting the phase of the clock signal, output from said oscillator, based on a comparison result output from said phase detector circuit;
• the clock signal, output from said phase shift circuit, being supplied as said clock signal for discrimination to said discriminator circuit.

A clock and data recovery circuit comprising:

• a first feedback loop at least including a first phase detector circuit for detecting the phase difference between a clock signal and a received data signal;
• a second feedback loop including a discriminator circuit supplied with said received data signal, and a second phase detector circuit for detecting the phase difference between the data signal, discriminated and output by said discriminator circuit, and said received data signal;
• and
• a clock recovery circuit for being controlled by said first and second feedback loops to output the clock signal recovered;
• the clock signal output from said clock recovery circuit being supplied as a clock signal for discrimination by said discriminator circuit.

A clock and data recovery circuit comprising:

• a first feedback loop including a first phase detector circuit for detecting the phase difference between an input reference clock signal and a recovered clock signal;
• and
• a second feedback loop including a discriminator circuit supplied with a received data signal and a second phase detector circuit for detecting the phase difference between the data signal discriminated and output by said discriminator circuit and said received data signal;
• a clock for discrimination of said discriminator circuit being supplied from a clock recovery circuit controlled by said first and second feedback loops.