System and method of executing program threads in a multi-threaded processor

A multithreaded processor device, comprising:

• a memory;
• a sequencer coupled to the memory;
• a stall controller within the sequencer;
• at least a first program thread within the memory;
• and
• at least a second program thread within the memory;
• wherein the at least second program thread is execution linked to the at least first program thread so that when the at least first program thread experiences a stall event, the at least second program thread is controlled in order to keep the at least second program thread execution linked to the at least first program thread.

A method of operating a digital signal processor device, the method comprising:

• detecting that a first program thread is execution linked to a second program thread;
• setting a first program counter to a first instruction of the first program thread;
• setting a second program counter to a first instruction of the second program thread;
• and
• executing the first program thread in a lock step manner with the second program thread so that each instruction of the second program thread is executed in a super cycle in which a corresponding instruction of the first program thread is executed.

A data register to control execution of two or more program threads of a multithreaded processor, the data register comprising:

• a first thread execution linking register;
• a first field within the first thread execution linking register, the first field associated with a first program thread;
• and
• a second field within the first thread linking register, the second field associated with a second program thread.

A data register set, comprising:

• a first thread linking register;
• a second thread linking register;
• and
• a third thread linking register;
• wherein each of the thread linking registers comprises:
• a first thread bit associated with a first program thread;
• a second thread bit associated with a second program thread;
• a third thread bit associated with a third program thread;
• a fourth thread bit associated with a fourth program thread;
• a fifth thread bit associated with a fifth program thread;
• and
• a sixth thread bit associated with a sixth program thread.

A portable communication device, comprising:

• a digital signal processor;
• wherein the digital signal processor includes:
• a first program thread;
• and
• a second program thread;
• wherein the second program thread is execution linked to the first program thread, such that when the first program thread experiences a stall event, the second program is controlled to maintain execution linkage to the first program thread.

A digital signal processor device, comprising:

• means for detecting that a first program thread is execution linked to a second program thread;
• means for setting a first program counter to a first instruction of the first program thread;
• means for setting a second program counter to a first instruction of the second program thread;
• and
• means for executing the first program thread in a lock step manner with the second program thread so that each instruction of the second program thread is executed in a super cycle in which a corresponding instruction of the first program thread is executed.