Automatic floorplanning approach for semiconductor integrated circuit

A floorplanning approach in hierarchical layout design of a semiconductor integrated circuit essentially composed of one or more black-box blocks each having at least input/output information at the block boundaries, the shape and area of the black-box block being set in advance, and one or more white-box blocks each having not only input/output information at the block boundaries but also information on components inside the block and connections for the components, the floorplanning approach determining the shape and area of a block based on result information of flat placement obtained by expanding a hierarchical structure, the approach comprising the steps of:

• (1) setting a shape of a polygon, a circle or an ellipse inside the black-box block as a core region of the black-box block, and performing the flat placement permitting placement position overlap between the black-box block and a component inside the hierarchy-expanded white-box block for the region of the black-box block other than the core region;
• (2) checking placement position overlap between the black-box block and a component inside the white-box block;
• and
• (3) changing the shape and area of the black-box block from those set in advance according to the overlap status,
• wherein the steps (1) to (3) are repeated in turn until a set condition is satisfied.