High reliability memory module with a fault tolerant address and command bus

A high-reliability memory arrangement with a fault tolerant address and command bus for use as a main memory that will achieve the degree of fault-tolerance and self-healing necessary for autonomic computing systems comprising;

• a memory interface chip;
• a memory controller;
• and
• a dual inline memory module having a register coupled to the memory interface chip and the memory controller via address/command lines together with check bits for error correction such that the memory controller sends address and command information to the register via the address/command lines together with check bits for error correction purposes to the register.

A server comprising:

• a memory interface chip;
• a memory controller;
• and
• a plurality of dual inline memory modules (DIMMs), each having a phase lock loop circuit chip, a error correction code/parity register chip and a plurality of dynamic random access memory (DRAM) chips, thereon, and
• said memory controller and said memory interface chip being coupled to said plurality of dual inline memory modules by data lines, clock lines, an address bus and a command bus.

A server memory structure comprising

• a dual inline memory module provided with selective redundant contacts;
• a phase locked loop;
• said dual inline memory module is provided with a 2 to 32 K bit serial EE PROM;
• and
• a multi-byte fault reporting register coupled to the memory interface and memory controller via an independent bus;
• means for reading said multi-byte fault reporting register bus;
• and
• real time error lines for reporting both correctable errors and uncorrectable error conditions.

An error correction code register comprising:

• a 28 bit 1:2 register segment;
• and
• an error correction code circuit and an error logic circuit for reporting errors and for correcting single bit errors to permit continuous memory operation independent of the existence of single bit errors;
• said register segment comprising a first set of differential receivers coupled to a check bit bus, a second set of differential receivers coupled to a data line bus and a plurality of input differential bit receivers and latch selection input differential receiver;
• each of said differential receivers having two inputs and a single output;
• a plurality of input multiplexers, a plurality of primary latches, a plurality of secondary multiplexers and a plurality of secondary latches;
• the first input of each differential receiver in said first set of differential receivers, said second set of differential receivers and said plurality of input differential bit receivers being coupled to a reference voltage source and the second input of each differential receivers being coupled to a respective input from said memory interface chip;
• each receiver in said first set having an input respectively coupled to a respective check bit line in said set of check bit lines and to a respective output connected through a respective check bit input multiplexer and a respective input latch to a single bit error correction/double bit error detection circuit circuit;
• each receiver in said second set having an input respectively coupled to a respective data line in said set of data lines and an output connected through a respective data primary multiplexer and a respective primary latch, a single bit error correction/double bit error detection circuit, a respective secondary multiplexer and secondary latch to an output line;
• a first input differential receiver having an input coupled to a check bit 0 signal line and an output coupled through a primary multiplexor and primary latch to a single bit error correction/double bit error detection circuit;
• second and third input differential receivers having their second input respectively coupled to Chip select lines /CS0 and /CS1 and their outputs coupled respectively to the first inputs of a pair of primary latches, the first and second inputs of a an input select NAND gate;
• the output of the NAND gate is coupled to the selection inputs of the primary multiplexors;
• a fourth differential receiver having an input coupled to a first clock enable signal source (CKE0) and an output coupled to a respective primary latch;
• a fifth differential receiver having an input coupled to a second clock enable signal sources (CKE1) and an output coupled to a respective primary latch;
• a sixth receiver having an input coupled to a first On Die Termination line signal line (ODT0) and an output coupled to a respective primary latch;
• a seventh Receiver having an input coupled to a second On Die Termination line signal line (ODT1) and an output coupled to a respective primary latch;
• and
• a receiver having an input coupled to the reset (/RST) signal line and an output to the reset input of all the primary and secondary latches.

A method of operating a server for detecting the status of a DIMM inserted therein to assure the DIMM can monitor the address and control bus integrity, and can correct errors on the address and control bus and report errors and log and count errors consisting of the steps of;

• accessing said DIMM using an industry standard IIC protocol and address input range sources (SA0, SA1, SA2),
• activating said DIMM to produce a byte of data which includes the contents of Byte 0, i.e.,
• Bit 7
• Bit 6
• Bit 5
• Bit 4
• Bit 3
• Bit 2
• Bit 1
• Bit 0
• RFU 0
• DIMM
• DIMM
• DIMM
• Mode
• Parity
• ECC error
• ECC error
• Address
• Address
• Address
• 1=ECC
• Error
• 1=UE
• 1=CE
• SA2
• SA1
• SA0
• 0=Pty
• 1=PERR
• stimulating the DIMM to echo back the input range sources (SA0, SA1, SA2) on bits four, five and six of said Byte 0, and
• applying a high signal level (a “1”) on bit 3 to provide a unique signature on bits four, five and six to determine if the signature matches a code sent to the DIMM.