Error detection in a logic device without performance impact

Abstract

An apparatus and method to perform error detection in a logic device without performance impact. The apparatus includes an Error Detection Device (EDD) coupled to a memory module and a processor. The memory module connects to the processor. As information transfers from the memory module to the processor, the EDD receives the same information and checks the information for errors. The information may be instructions, data, or control sequences. If the EDD does not detect any errors in the information, the processor is allowed to complete execution of the information. If the EDD detects an error in the information transferred from the memory module, an action is sent to the processor before the erroneous information is executed. Because the error checking is done by the EDD at the same time as the transfer of information from the memory module to the processor, the performance of the system is not impacted.

Dependencies are inferred from the claim text.